Continuous-Time Analog Filtering: Design Strategies and Programmability
in CMOS Technologies for VHF Applications

171
control the HS transconductance from 270 to 452 μA/V, and changes from 40 to 100 μA in
the FC topology control the transconductance from 550 to 800 μA/V.

200
250
300
350
400
450
-450 -350 -250 -150 -50 50 150 250 350 450
V
c
(mV)
IBIAS=180uA
IBIAS=135uA
IBIAS=90uA
IBIAS=45uA

480
520
560
600
640
680
720
760
800

nominal bias current of 100 μA per branch.
The dimensions of the transistors were chosen in order to cover all the design requirements
obtained in this chapter, leading to a complete sweep of the discrete step by varying the bias
current. In this way, for the HS implementation, the operation point is located at 90 μA and
the bias current adjustment is possible from 45-180 μA. However, for the FC
implementation, the operating point is located at 100 μA, covering the digital step by
varying the bias current from 20-110 μA. In this way, the discrete tunability requirement is
obtained but the FC transconductance value at the operation point is maximised.
8.1 Layout strategy
A careful layout has been drawn out to obtain all the characteristics associated with the
proposed design accurately and demonstrate the feasibility of the intended approach. As
g
m
(μA/V)
g
m
(μA/V)
Advances in Solid State Circuits Technologies

172
stated below, we have taken special care to get rid of the unwanted effects related to
parasitic elements and mismatching (Baker et al., 1998; Hastings, 2001). All the designs have
been carried out taking into account the specific design rules for high frequency operation,
which are highly appropriate for obtaining good matching between components.
Interdigitized and common-centroid layout techniques have been considered to reduce the
variations of threshold voltage, which are associated with gradients in gate-oxide thickness.
Guard rings have been included in the design with the aim of reducing substrate noise.
Bond-pads have also been carefully laid out and, in this way, input and output pins have
been placed as far as possible between them. Balanced structures provide outstanding
benefits, but they are strongly dependent on the symmetry of the circuit. Consequently,

b
1
b
0
Continuous-Time Analog Filtering: Design Strategies and Programmability
in CMOS Technologies for VHF Applications

173
same figure, by varying the bias current source from 45 to 180 μA for a fixed digital word,
the transconductance value is modified, providing complementary fine tuning of the
frequency. All discrete steps are covered and, in consequence, a frequency span of 25-185
MHz can be provided. The maximum frequency error is obtained at the maximum digital
word where a deviation of 6 % is obtained from the 7:1 ratio.

10
50
90
130
170
210
250
290
45 65 85 105 125 145 165 185
7gm
6gm
5gm
4gm
3gm
2gm
1gm

digital word where a deviation of 5 % is obtained from the 5:1 ratio.
The next step is to demonstrate constant linearity by means of a constant THD over the
entire programming range. Figs. 18 and 19 show the THD variation as a function of the
differential output current for all the digital words. THD was measured for a sine input
current of 10 MHz (a) and for the unity-gain frequency (b) in both topologies. These figures
show the expected THD dependence, studied above in section §6: lower bias currents or
higher input signal amplitudes lead to higher THD values. A corner parameter analysis was
carried out following the guidelines provided by the design kit manufacturer of the ‘AMI
Semiconductor C035M Design-Kit’ and the worst-case analysis for the HS integrator was
obtained. This distortion study gave 1 % of THD for a differential input signal of 56 μA and
10 MHz. Experimental results for the design, shown in Fig. 18, lead to a differential input
current of 50 μA in the same situation. For the FC approach, the expected value for 1 % of
THD was a differential input signal amplitude of 37 μA and 10 MHz; and the experimental
results (Fig. 19), give an amplitude of 35 μA.
The post-layout simulated result for the input-referred noise integrated from 0 to 30 MHz in
the HS topology was 11.2 nA
rms
. Hence, the dynamic range, defined as the input signal
amplitude at 1 % THD divided by the total noise level integrated over 30 MHz, is 70 dB. In
the FC structure, the input-referred noise integrated from 0 to 40 MHz was 8 nA
rms
. Hence,
the dynamic range, defined as the input signal amplitude at 1 % THD divided by the total
noise level integrated over 40 MHz, is also 70 dB.
In summary, frequency is adjusted in a coarse discrete way by connecting identical
transconductors in parallel and with fine continuous tuning by varying the biasing current.

ω
t
(MHz)

-70
-65
-60
-55
-50
-45
-40
-35
0,04 0,12 0,20 0,28 0,36 0,44
iout/Ibias
THD(dB) @ Wt=25 MHz
4gm
2gm
gm

(a) (b)
Fig. 18. THD versus differential output current in the HS integrator for three different digital
words: (a) ω(input)=10 MHz, (b) ω(input)= ω
t
(25 MHz for 1g
m
).
-65
-60
-55
-50
-45
-40
-35
0,04 0,08 0,12 0,16

).
The feasibility of the programmable array of transconductors has been proven in a 3-bit
programmable integrator obtaining frequency scaling as expected. All the specifications in
both transconductor implementations are summarized in table 7. The main advantage of the
topology proposed was the inherent enhancement of the dc-gain, provided through the
existing positive feedback compensation (negative resistance).
The HS design condition was very difficult to achieve because technological process and
temperature variations are expected to be greater than the small changes required in this
topology. As expected, by varying the external control for this negative resistance, no
change was obtained for the dc-gain. The post-layout simulated dc-gain was a variation of
15 dB between the minimum (40 dB) and the maximum (55 dB), with a maximum CMRR of
60 dB. The experimental results lead to a differential dc-gain of 30 dB with no change with
the value of the negative resistance and a CMRR greater than 35 dB over the entire
frequency range. Therefore, in this case, there is no control on the dc-gain of the system.
The design condition for the FC topology is less restrictive and two different
implementations have been fabricated. The post-layout simulation results in both cases
showed a dc-gain control of 15 dB from 30 to 45 dB and a maximum CMRR of 50 dB. The
first implementation has been designed with the same dimensions for the M
N
transistors
Continuous-Time Analog Filtering: Design Strategies and Programmability
in CMOS Technologies for VHF Applications

175
involved in the negative resistance, and similar results are obtained as in the HS topology.
There is no external dc-gain control and an experimental value of 26 dB and CMRR of 33 dB
are obtained. In the second one, where a pre-designed mismatching is included between M
N

transistors involved in the negative resistance, a variation of 12 dB (from 26 to 38 dB) for the

15
25
35
0 1 10 100 1000
frequency ( MHz)
gain (dB)

Fig. 20. Experimental dc-gain control for the FC transconductor with a pre-designed
mismatching between M
N
transistors involved in the negative resistance.
9. Conclusion
This work describes a new approach for implementing digitally programmable and
continuously tunable VHF/UHF transconductors compatible with pure digital CMOS
technologies and suitable for HDD read channel applications. The cell is suitable for low-
voltage operation over an extended frequency range. The programmability exhibited by the
transconductor is due to the use of a generic programmable structure that gives a G
m
digital
control as a parallel connection of unit cells, and the total parasitic capacitances are
maintained constant thanks to the specific design of the unit cell: a cascode stage with
12 dB
Advances in Solid State Circuits Technologies

176
dummy elements. This transconductor could be used in any kind of G
m
-C filter, thus
providing a very wide range of programmable CT filters. The fully-balanced current-mode
G

Felt E.; Narayan A. & Sangiovanni-Vincentelli A. (1994). Measurement and Modelling of
MOS Transistors Current Mismatch in Analog ICs, Proceedings of the IEEE/ACM
International Conference on Computer Aided Design, pp. 272-277, ISBN: 0-8186-6417-7,
San Jose, California, November 1994, Broadway, New York.
Gray P.R. & Meyer R.G. (2001). Analysis and Design of Analog Integrated Circuits, 4
th
Edition,
John Wiley & Sons, Inc., 2001.
Gregor R.W. (1992). On the Relationship Between Topography and Transistor Matching in
an Analog CMOS Technology. IEEE Transactions on Electron Devices, Vol. 39, No. 2,
1992, 275-282, ISSN: 0018-9383.
Hastings A. (2001). The Art of Analog Layout, Prentice Hall, Inc., 2001.
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in CMOS Technologies for VHF Applications

177
Mohan S.S.; Hershenson M.; Boyd S.P. & Lee T.H. (2000). Bandwidth Extension in CMOS
with Optimized On-Chip Inductors. IEEE Journal of Solid-State Circuits, Vol. 53, No.
3, March 2000, 346-355, ISSN: 0018-9200.
Nauta B. (1993). Analog CMOS Filters for Very High Frequencies, Kluwer Academic Publishers,
1993.
Otín A.; Celma S. & Aldea C. (2004). Digitally Programmable CMOS Transconductor for
Very High Frequency. Microelectronics Reliability Journal, Vol. 44, No. 5, 2004, pp.
869-875, ISSN: 0026-2714.
Otín A.; Celma S. & Aldea C. (2005). A 0.18 μm CMOS 3
rd
-order Digitally Programmable
G
m
-C Filter for VHF Applications. IEICE Transactions on Information and Systems,

Wakimoto T. & Akazawa Y. (1990). A Low-Power Wide-Band Amplifier Using a New
Parasitic Capacitance Compensation Scheme. IEEE Journal of Solid-State Circuits,
Vol. 25, No. 1, February 1990, 200-206, ISSN: 0018-9200.
Wyszynski A. & Schaumann R. (1994). Avoiding Common-Mode Feedback in Continuous-
Time G
m
-C Filters by the Use of Lossy-Integrators. Proceedings of the IEEE
Advances in Solid State Circuits Technologies

178
International Symposium on Circuits and Systems, Vol. 5, pp. 281, Vancouver
(Canada), May 1994.
Zele R.H. & Allstot D. (1996). Low-Power CMOS Continuous-Time Filters. IEEE Journal of
Solid-State Circuits, Vol. 31, No. 2, 1996, 157-168, ISSN: 0018-9200.
9
Impact of Technology Scaling
on Phase-Change Memory Performance
Stefania Braga, Alessandro Cabrini and Guido Torelli
Department of Electronics, University of Pavia
Italy
1. Introduction
Nowadays, non-volatile storage technologies play a fundamental role in the semiconductor
memory market due to the widespread use of portable devices such as digital cameras, MP3
players, smartphones, and personal computers, which require ever increasing memory
capacity to improve their performance. Although, at present, Flash memory is by far the
dominant semiconductor non-volatile storage technology, the aggressive scaling aiming at
reducing the cost per bit has recently brought the floating-gate storage concept to its
technological limit. In fact, data retention and reliability of floating-gate based memories are
related to the thickness of the gate oxide, which becomes thinner and thinner with
increasing downscaling. The above limit has pushed the semiconductor industry to invest

and the read operation by means of a simple analytical model which takes the electro-
thermal behavior of the PCM cell and the phase change phenomena inside the chalcogenide
alloy into account.
2. Working principle of the PCM cell
The working principle of a PCM cell relies on the physical properties of chalcogenide
materials, typically Ge
2
Sb
2
Te
5
(GST), that can switch from the amorphous to the crystalline
phase and vice versa when stimulated by suitable electrical pulses. Basically, a PCM cell is
composed of a thin GST film, a resistive element named heater (TiN), and two metal
electrodes, i.e., the top electrode contact (TEC) and the bottom electrode contact (BEC). Only
a portion of the GST layer, which is located close to the GST-heater interface and is referred
to as active GST, undergoes phase transition when the PCM cell is thermally stimulated. In
particular, in this work we focus our attention on the Lance heater geometry (Pellizzer et al.,
2006), which is essentially composed of a thin layer of GST alloy and a pillar-shaped heater,
as shown in Fig. 1. In the reference Lance heater cell implemented in the 90 nm technology
node, the GST thickness t is 70 nm, the GST-heater contact area A is 3000 nm
2
, and the heater
height h is 180 nm.
The typical V-I characteristic of the PCM cell in the amorphous (RESET) and the crystalline
(SET) state is shown in Fig. 2. Consider the case of a cell in its full-SET state: the differential
resistance of the cell decreases as the applied voltage increases. This effect is due to the
contribution of the crystalline GST to the cell resistance. In fact, the crystalline GST
resistivity decreases with increasing electrical field inside the material.


order to provide the device with enough energy to induce phase change. Since phase
transitions are thermally assisted, in PCM devices Joule heating is exploited to raise the
temperature inside the chalcogenide material to the required value. The crystalline-to-
amorphous phase transition is obtained by applying a high-amplitude electrical pulse to the
cell so as to bring the temperature of the active GST material above the melting point T
m
(about 600 °C) (Peng et al., 1997), and then quickly cooling the memory cell, in order to
freeze the GST material into a disordered (i.e., amorphous) structure. A pulse duration on
the order of few tenths of ns is sufficient (Weidenhof et al., 2000). The amorphous-to-
crystalline phase transition is obtained by applying an electrical pulse with a lower
amplitude and a longer time duration. In this case, the amorphous material is heated to a
temperature below the melting point but above the crystallization temperature, that is the
temperature necessary to activate the crystallization process in the required time scale
(typically an the order of 100 ns). This way, the thermal energy is able to restore the
crystalline lattice, which is a minimum-energy configuration. Typical electrical pulses for
SET and RESET operations are shown in Fig. 3.
Advances in Solid State Circuits Technologies

182
I
melt
I
cry
t (s)
fast
quenching
I(A)
GST
melting
RESET

3. Programming operation
We analyzed first the impact of technology scaling on the programming operation, focusing
our attention on the electical power (hereinafter referred to as programming power). The
maximum programming power is obviously required by the RESET operation, where the
highest temperatures are needed to melt the active GST volume. The RESET pulse duration
must be higher than the minimum required time for melting \cite{Weidenhof00}, while the
cooling time must be short enough to prevent the crystallization process from taking place.
The minimum current required to melt a portion of the active GST layer is referred to as
melting current, I
m
. When the current flowing through the memory cell during a write
operation is higher than I
m
, the obtained RESET resistance increases with the amplitude of
the current pulse. In fact, the maximum temperature inside the cell increases with the pulse
amplitude, thus leading to the amorphization of a larger GST volume.
The maximum temperature reached inside a Lance heater cell of given sizes can be
estimated by means of an approximated electro-thermal model. In general, the temperature
increase in the active GST volume is due to the current flow both through the heater (heater
heating) and through the GST layer itself (GST self-heating). Nevertheless, GST self-heating
can be neglected when considering high-amplitude RESET pulses. In fact, the resistance of
the GST layer (both in the crystalline and in the amorphous state) is negligible with respect
to the heater resistance due to high-field effects (the PCM cell is operated in the ON region).
Thus, in this case we can estimate the temperature profile inside the PCM cell by
considering only the Joule power generated inside the heater when a current I flows
through the cell. We assume, for simplicity, a cylindrical geometry of the heater and
calculate the temperature along the cell axis. The power generated in a volume A
δ
z


th GST u
R
TR RzRz Q
RRz
δ
δ
⎡⎤
=+
⎣⎦
+

&

(1)
where
()
h
hz
u
A
Rz
κ
−
=


and ()
h
z
d

,,
2( )
th GST th h
h
th GST th h
RR
Ih
TT
AR R
ρ
=
⋅+
+
(2)

,,0
1
()
2
JthGSTthh
QR R T
=
+&
(3)
In the above equations, T
0
is room temperature,
2
h
Ih

hh
th GST th h
RR
TT
I
k
RR
ρ
+
−
=⋅ (4)
In order to estimate the dependence of R
th,GST
on the geometrical features of the memory cell,
we simulated the temperature profile along the cell axis inside the GST layer (Fig. 5a). Fig.
5b shows the simulation results for different values of the GST layer thickness obtained with
our previously proposed 3D model (Braga et al., 2008). It can be noticed that the
temperature decreases almost linearly inside the GST layer with increasing distance from
the GST-heater contact. Moreover, the accuracy of the linear approximation increases as the
ratio between the GST layer thickness and the heater radius decreases. Since this behavior
suggests that heat flow inside the GST is substantially directed along the cell axis, from the
heater-GST interface along the cell axis, a reasonable approximation for the thermal
resistance of the GST layer is R
th,GST
=
GST
t
A
κ
, where


Due to fabrication process constraints, heater geometries with a high aspect ratio (i.e.,
geometries having a high ratio between the GST-heater contact diameter and the heater
height), may not be easily manufacturable. Several fabrication solutions have been proposed
to overcome lithographic limits and, thus, realize heater structures with minimized contact
area (Lam, 2006; Pirovano et al., 2008). In the following, we will consider heater geometries
with a high aspect ratio with the purpose of investigating the scaling perspective, even if
they may require advanced fabrication techniques. Given a scaling factor
ε < 1, I
m
turns out
to be proportional to
ε in the case of isotropic scaling, where all the linear dimensions are
scaled by the same amount, while I
m
∝ ε
2
in the case of shrinking, where only planar
dimensions are scaled. The comparison of melting current reduction in the cases of isotropic
scaling and shrinking is shown in Fig. 6.
In order to compare PCM cells having different dimensions, we chose to consider the full-
RESET state to be achieved when the maximum temperature inside the PCM cell reaches a

Impact of Technology Scaling on Phase-Change Memory Performance

185

Fig. 5. Cell structure (a) and simulated temperature Maps inside a Lance heater PCM cell
with different values of GST layer thickness: 40 nm, 70 nm, and 100 nm (b). Notice that the
temperature profile is almost linear inside the GST layer. The maps were obtained by means


Fig. 6. Melting current reduction in the case of isotropic scaling (left) and shrinking (right).
The dimensions are scaled with respect to a reference lance heater cell realized in 90 nm
technology
Advances in Solid State Circuits Technologies

186
500 1000 1500 2000 2500 3000
90
100
110
120
130
140
150
160
170
180
200
200
400
400
400
6
00
600
600
800
800
80

800
1000
RESET current (μ A)
Contact area (nm
2
)
30 40 50 60 70
450
500
550
600
RESET current (μ A)
GST layer thickness (nm)
h=180 nm
t=70 nm
A=1600 nm
2
t=70 nm
A=1600 nm
2
h=180 nmFig. 8. RESET current dependence on the geometrical parameters of the memory cell.
predetermined value, T
RST
, which is obtained with a current pulse of amplitude I
RST
.
Typically, I

100
200
300
400
500
600
Cell axis
Temperature (°C)Analytical model
3D model
Heater
GST layer

Fig. 9. Comparison of the thermal profile along the cell axis obtained by means of the
analytical model and the 3D finite-element model.

Heater thermal conductivity
κ
h

36
W
mC
D

GST layer thermal conductivity
κ
GST

used in the compact model was set higher than the actual physical value.
4. Read operation
The GST layer undergoes crystalline to amorphous phase transition in the region where the
temperature exceeds the melting point. As pointed out above, the temperature profile along
the cell axis inside the GST decreases almost linearly with the distance from the GST-heater
interface. By approximating the thermal profile inside the GST along the cell axis with a
straight line, we derived the analytical expression for the thickness of the amorphous cap x
a
obtained when a full-RESET pulse is applied to the cell:
Advances in Solid State Circuits Technologies

188

0
()
RST m
a
RST
TT
xt
TT
−
=
−
. (6)
Thus, the thickness of the amorphous cap obtained by means of the RESET operation is a
fraction f =
0
()
RST m


C
SET h
t
RR
A
ρ
=+
, (8)
where
ρ
C
is the resistivity of crystalline GST.
When considering the current sensing approach, we can calculate the minimum and the
maximum read current:

,
,
read
rd min
RST
V
I
R
= (9)

,
,
read
rd max


read
re
f
E
E
RST
Re
−
∝ , (11)
Impact of Technology Scaling on Phase-Change Memory Performance

189
where E
ref
is the electrical field which activates the electrical resistivity inside the amorphous
GST. The value of V
read
must be chosen so as to ensure that the PCM device is operated in the
read region (OFF zone) and the electrical field during readout is below the critical switching
field for every considered cell size. In this respect, we chose V
read
= 0.3 V and calculated the
cell resistance and the read current for both the SET and the RESET state. E
ref
was set to 30M
V/m (Buckley & Holmberg, 1974).
Several studies (Adler et al., 1980; Buckley & Holmberg, 1974) have shown that V
th
decreases

t=30nm, h=90nm
t=70nm, h=90nm
t=30nm, h=180nm
t=70nm, h=180nm
SET
RESET
Fig. 10. Constant voltage approach: read current as a function of the contact area A for
different values of GST layer thickness t and heater height h. The read voltage is assumed to
be 0.3 V.
Advances in Solid State Circuits Technologies

190

500 1000 1500 2000 2500 3000
10
–6
10
–5
10
4
Contact Area (nm
2
)
Read current (µ A)t=30nm,h=90nm

change memory cells by investigating its effects on both the programming current and the
width of the read window. To this end we derived a simplified analytical model of the PCM
cell electro-thermal behavior and validate it by means of a 3D finite-elements model of the
PCM cell. We considered both constant field and constant voltage scaling approaches. Our
study highlights the program-read tradeoffs challenges which aggressive scaling arises and
provides analytical insight in the scaling mechanisms.
Impact of Technology Scaling on Phase-Change Memory Performance

191
6. Acknowledgements
This work has been supported by Italian MIUR in the frame of its National FIRB Project
RBAP06L4S5.
7. References
Adler, D., Shur, M. S., Silver, M. & Ovshinsky, S. R. (1980). Threshold switching in
chalcogenide-glass thin films, Journal of Applied Physics 51(6): 3289–3309.
Braga, S., Cabrini, A. & Torelli, G. (2008). An integrated multi-physics approach to the
modeling of a phase-change memory device, Proc. of Solid-State Device Research
Conference, pp. 154–157.
Braga, S., Cabrini, A. & Torelli, G. (2009). Theoretical analysis of the RESET operation in
phase-change memories, Semiconductor Science and Technology, 24 (11) 115008
(6pp).
Buckley, W. D. & Holmberg, S. H. (1974). Evidence for critical-field switching in amorphous
semiconductor materials, Phys. Rev. Lett. 32(25): 1429–1432.
Geppert, L. (2003). The new indelible memories, IEEE Spectrum 40(3): 48–54.
Ielmini, D. & Zhang, Y. (2007). Evidence for trap-limited transport in the subthreshold
conduction regime of chalcogenide glasses, Applied Physics Letters 90(19):
192102.
Kim, D H., Merget, F., Först, M. & Kurz, H. (2007). Three-dimensional simulation model of
switching dynamics in phase change random access memory cells, Journal of Applied
Physics 101(6): 064512.

2
Sb
2
Te
5
films, Journal of Applied Physics 88(2):
657–664.
10
Advanced Simulation for
ESD Protection Elements
Yan Han and Koubao Ding
ZJU-UCF Joint ESD Lab, Zhejiang University, Hangzhou 310027,
P.R.China
1. Introduction
Electrostatic discharge (ESD) failure is one of the most important causes of reliability
problems, therefore the design and optimization of ESD devices have to be done. To achieve
very short time to market and reduce the development effort, one tries to make use of the
benefit of simulation tools. However, due to the complex physical mechanism of ESD events
and the hard mathematic calculation in the snapback region, simulation of the I-V
characteristic of ESD protection devices has been proved to be difficult.
This chapter aims at providing a systematic way to ESD simulation, including the process
simulation, device simulation and circuit level simulation. Process/device simulation offers
an effective way to evaluate the performance of ESD protection structures. However, to
prevent the injury of ESD, protection circuits are used sometimes. Therefore circuit level
simulation is needed.
There are several process/device simulation tools in the world, the most widely used of
which include Tsuprem4/Medici, Athena/Atlas and Dios/Mdraw/Dessis. Tsuprem4,
Athena and Dios are process simulators, while Medici, Atlas and Dessis are device
simulators. Mdraw is an independent mesh optimization tool, and the similar functions are
integrated in device simulation tools, such as Medici and Atlas. The process and device

LEXP (lexp), LEXPOW (α). The range of parameters that must be specified for each of the
single primary distribution functions are shown in Table1. In Table1, x means the parameter
must be a real number, x0 means the parameter must be nonnegative, > 0 means the parameter
must be positive, and ∅ means the parameter is not allowed for the particular function. Once
the implanted element, energy, dose, tilt and rotation of an implantation process step are
defined by users, the relevant parameter set will be looked up in implant tables. With proper
parameter set, the impurity distribution will be calculated subsequently. If users have data
fitted to experiments, the parameter set can be defined in implantation command. Table 1. Range of parameter specification for the distribution functions
According to the simulation results, the single primary distribution functions can be divided
into 3 groups. Group1 contains Pearson distribution function; group2 contains P4, P4S, P4K
distribution functions; group3 contains Gauss, GK, JHG, JHGK distribution functions. Fig.1
(a) shows the 2D impurity distribution with different implantation models; Fig.1 (b) shows
the impurity distribution along Y direction. From Fig.1 (a) and Fig.1 (b), we can see that
functions in the same group have similar simulation results. Actually, the distribution
functions in group3 are usually used in deep implantations, such as WELL implantation in
CMOS process; and the distribution functions in group1 and group2 are usually used in
shallow implantations, such as drain/source implantation in CMOS process.
In order to obtain more accurate simulation result, we should take ion channeling into
consideration. Then the dual primary distribution functions should be used. That is, the profile
Advanced Simulation for ESD Protection Elements

195
is divided into two components, the first components representing the profile of ions, which
don’t channel, and the second one representing the channel ions. A dual primary distribution
function is obtained by specifying two single primary functions for the two components
mentioned above. It can be defined in the implantation command following the format: