Hierarchical Reuse Model 21
Figure 1.9.
time.
TSO storage pools: cache performance as a function of average cache residency
Figure 1.10.
residency time.
OS/390 system storage pools: cache performance as a function of average cache
22
CICS: On
-
line Virtual Storage Access Method (VSAM) database storage
under Customer Information and Control System (
CICS) file control. This
variety of application accounted for the largest single contribution to the
total storage seen in the survey.
IMS: On
-
line Information Management System (IMS) database storage (more
precisely, storage for databases accessed via the Data Language I (
DL/I)
database access language).
TSO: Storage for interactive users running under the Time Sharing Option
(
TSO).
System: Control files, program libraries, logs, and data used for system
administration (Spool, scratch, and paging data were excluded from the
system category).
This author’s reading of Figures 1.4 through 1.10 is that, if it is desired to
ensure that “cache friendly” applications (at a minimum) receive substantial
benefits from the cache, an objective for T of at least 30–60 seconds can be
recommended. If, in addition, it is desired to get substantial performance gains

was made of the facilities provided in these storage controls for limiting the
THE FRACTAL STRUCTURE OF DATA REFERENCE
Hierarchical Reuse Model 23
use of cache memory to identified volumes, while “turning off” access to the
cache by other volumes.
Cache sizes increased sharply with the introduction of the 3880 Model
23 storage control (maximum cache size 64 megabytes), and again with the
3990 Model 3 storage control (maximum cache size 256 megabytes). At
the beginning of the 1990’s, a typical storage control was configured with
approximately 120 gigabytes of storage capacity, and an
I/O demand of, say,
300
I/O’s per second. Both reads and writes were cached. By this time, memory
management techniques had improved so that, when staging data as the result
of a miss, it was possible to allocate only enough memory for the requested
record and subsequent records on the track (if a request then occurred for data
before the requested record, a fairly unusual event, this would cause a so
-
called
“front
-
end miss”). Thus, the size of the most common track image at this
time was 0.057 megabytes
2
, but we shall assume z = 0.04 megabytes (the
approximate memory allocation required, on average, for a stage). During
this time, (1.20) would suggest that a typical storage control should have been
configured with 0.04 x 0.7 x 300 x 30
0.75
= 108 megabytes of cache memory.

In moving an application from an older storage control to a newer one,
the system administrator is well advised to keep an eye on the average cache
residency time being delivered to applications, in order to avoid placing current
service level agreements at risk. This can be done using cache performance
measurements which are standard in
VM and OS/390 environments, together
with the estimates of the average cache residency time presented previously in
Subsection 4.2.
4.5 SEQUENTIAL WORKLOADS
While on the subject of residency time objectives, it is appropriate to include
a brief discussion of sequential workloads. Sequential work plays an important
role in batch processing, particularly during off
-
shift hours. The characteristics
and requirements of sequential
I/O contrast sharply with those of random
-
access
I/O, and in general sequential work must be analyzed as a special case, rather
than using the same probabilistic or statistical methods that apply to a random
-
access environment.
The next request for a given item of sequential data tends to be either
immediate, or a relatively long time in the future. As a result, most cached
storage controls perform early demotion of sequential data residing in the cache;
the memory for such data is typically freed long before the data would have
progressed from the top to the bottom of the LRU list. Storage controls also
typically use sequential prestage operations to bring data that appears to be due
for sequential processing into cache in advance of anticipated requests. The net
result of sequential prestage, coupled with early demotion, is that sequential

is necessary to consider what impact should be expected from such buffers.
It is not so much the performance of the processor buffers themselves which
complicate the picture developed so far, since their performance can be de
-
scribed by the methods of analysis already discussed. Instead, it is necessary
to examine the impact that processor buffering has on the
I/O requests being
made to the storage subsystem.
Typically, write requests issued by
OS/390 applications result in update oper
-
ations in both the processor buffer area and the storage subsystem, since it is
necessary to ensure that the new information will be permanently retained (the
new data must be hardened), One copy of the data, however, is sufficient to
satisfy a read request. For this reason, we must expect some read hits to occur
only in the processor, which otherwise would have occurred in storage control
cache.
The effect of this on the cache miss ratio is easiest to see when the single
-
reference residency time in the processor is shorter than that in the cache, i.e.,
when τ
c
≥ τ
p
, where the subscripts c and p are used to denote processor and
storage control cache memories, respectively. In this case, all the hits in the
processor overlap with hits that would have occurred in the cache by itself,
assuming that the cache’s single
-
reference residency time is held fixed. The