begin
end
component
component
Al'!D2_GATE
purt
(
10.
II , in IllT;
0;
uut lllT
);
end
component:
U L
XOICGATE
port
map
( Ill. I I. S
);
\]2,
AND2JiATE
port
map
(IO.lI.
CO);
end
STRUC[URE;
Moi
thimh
ph.'in

;
out
fliT
);
end
XOR_GATE;
architecture
BEHAVIOR
of
XOR_GATE is
hcgin
0<=
10
xor
1\
arfer
\0
ns:
end
BEflA Y[OR;
Bicu
dicn
e:'lu
true cua Gte
phii.ll
cap thiel
1<.6
<'mh
hu'ong tai
qua

nhCrng
Ih111lh
phfin 6
mue dang xc\. Bi6u elien
cUu
true
ella kicn true ehu'a danh
siich cae
h('1p
(kn.
6
Illt:l'e
thfip nh[it ella qu,i
trlnh phall t{lch. ta ph:li
1110
la
h:l1lh
vi
Clla
cae
ph
fin
It'r
nam trang thiet
kc
c'5
muc
nay.
Qm\.
Irlnh phan

vi
ella
cae
th~t'e
the thea trinh tl! ma
1116
hinh lTIi.ICh
, ,e
dU\1C
mo ph('mg.
149
3.
Cae
g6i thiet
kc
M~le
dfch
ehfnh
ella
cae
g<11
la
1(lp
h\1p
cae
phan
tll'
C<1
the dllllg
chung

cae
don vi
thiet
kc
dung
den
khi
SLf
dung g6i.
Tht'mg
tlnii'mg:
ph[\n
khai
h<'lo
chua
m(lt
so
ki~u
clt11i¢u
chung,
ceie
ht1ng
\"~11ll6
1;1
ella
dc
chVtmg
tdnb
COil.
Ph:ill lh,tn gai

con
dU\1C
1116
1:1
trong g(li.
Vi
cll.t,
ta
co
khai bao g6i nhu sau.
Cioi
nay khaJ
hilO
111~'it
StS
ki~u.
hic'n, h,lng
V,I
chunng trinh con.
pllckage EX_PKG
is
subtype
INT8 is INTEGER
range
0 to 255
constant
?ERO
: INT8 :=0 :
(.'onstant
MAX : INT8

procedure
lnercemcnt
( v41riable Dala: inout INT8 ) is
begin
end
if
if (
Count
>=
MAX)
then
Count
:= ZERO:
else
Count
:= Coullt +
1·
end Incrccm :nt;
end
EX-PKCJ:
4.
C{lC
cau
hlnh
M{)t
tlwe the
co
the:
co
mot

thiet
kl:".
elll
hlnh
eho phep gtm
de
phien ban eua
thl!C
the yito
nhCrng
kicn
Ink
kh,\c
nhau.
Glu
hlnh
el"mg
eo the
duc.~e
Sli"
dung
de
thay
the"
me)t
deh
nhanh
ch6ng
de
ph;\n

{ ((ic_pllltll
1/1
(11(1
C{]II-'Iillh I
end
for;
Vi tu pillin
Jlul/Ju/o
_
Clia
__
c(/'lI_hillil eho phep
du
hlnh
Slr
dl!ng
de
phfil1
tll
trong
de
goi
vii
de
tlnl'vicn.
Vi tv
dlk
rd
Cli(/JI/()I"
X<.lc

hung
cau
hlnh nay,
chung
ta thay:
STRUcnJRE
ehi
to'i
kien true eoa thl!c
Ih6
FULL_ADDER dUde (Ut cau
hlnh.
HA 1 V:l
HAl:
Iii
cae
t1we the gan voi
thl!C
the
HALF
_ADER
ella kicn
tn.k
STRUCTURE
Hong thu
\'i~n
WORK.
151
Phltn
ban OR I

\'!
thiet
kC'
sc
dUQ'c
luu
giu'
trotH!
C{tC
thu
vitn
de
sU:
dun"
sau
n~IY.
Tim \'len thiet
kc
co the chefa
nilu"llo
~
. ' c
_,
c
phein
tLr
tilu \'i¢n sau:
Goi : i:'lllhlrng
m()
ta, khai b,io

vj
tilu'
\'ien Iii dIe
e<.'iu
true
YHDL
co
the
dUQ'e
ph,ln tfeh rieng
r0
thco trlnh
11,1'
nh[11
d!nh. Vi dl.l, tlwc the ph,ii
dUQ'e
ph,ln tfeh
truCic
kil'"n
true
eua chung:
dc
gOI
phai
dU\1C
ph:111
tich
truCK
khi
UU\K

sc
dU\K
bien d!ch
Vi:I
eh(ra
vilO
11m
vi¢n
"WORK".
Vi
d~l,
knh
\iC My-Design.vhd
sc
ki~lll
tra eu phap cillrung trinh ntun trong t¢p "My-Dcsign.vhd",
d1eh
L
_B~9~p~h~a_n~1
-+
tfch _
[
j library-1
[IEEE
-
[ STD
-
WORK
Thllv,en
[

dU'(ie
dli'<t
\'ilO!J':
me)
p!JClIlS_
cillf(mg trlnh
clo
r()i
ehlb
vilo
thu vi¢n
"WORK".
Illnh
6.10 chi
ra
de
phU'o)lg
thue slr
cll;lllg
cae
Ihu'
\'i~n
thiet
k~
trong ngon ngiI
VHDL.
l\gon
llgU
VHDL
c6

giii
tri ban d:iu mil
Ch(lllg
sC
nh(lll lrong qua trlnh
I1H1
phcmg.
1.
Cae
d6i
tut,mg
du
li~u
Trong ngon
ngCf
VHDL
nglf0i
1<1
p\},ln
hi¢1
ha loai d6i
1lH,:ing
dCi
li~u:
htlllg.
hi~n
\'~I
tin hi¢u. Cac d6i
1L1l)'ng
du'C)'c

ntn
trong
qu<i
Irinh
thve
hi~ll
va sau
d6
gi,i lri clla h,\ng khong lhay
(h~i.
Htlllg co the
dL10c
khai
b{1O
trong
cUc
gai. timc Ihe, kie'n truc, cillf(mg lrinh
con. khoi
Va
qu'.l
trlnh.
Cll
ph<.ip
kiwi
bao
hung:
constant
{ell
hiing
.

li¢u
dung
d~
clitIa
nhCfng
kc',
qU~l
trung
gian. Bien
chi
c6
the dm!c kiwi o.io ben Irong cac
qua
Idnh
hO~lc
chuang
trinh
con.
Bien
\uon
eli
doi \'6i
kiC:u.
do d6 bien rh,'ti
dlt'(K
kiwi baa
kiC:u.
xac d!nh
khOi.lng
gi{)'i

belo
nhu
sau.
Vi
d~l,
Co
Tin
hiell
variable
Temp:
ilIT_
VECTOR
( g
duwnto
0 )
variahle
Delay: INTEGER
ran~e
0
to
15
:=0:
Tin hieu
l~l
dtii
w0ng
du li¢u dung
de
ke't
n6i

tO~IJl
Cl.IC
).
khai b,io tlll!e th6 ( khi do tin hi¢u
b
tin
hi~Ll
toan
CL.lc
eLla
tht!c the l. khai hao kicn
tnk
( tin hi¢u sc
1;1
tin
hl¢U
tO~1l1
clie ella ki6n
true)
V;:I
trung khai. Cae tin hi¢u
c6
thc
dU\K
SLf
dung
nlurng k.h6ng the
(ILrqe
khai bao trong c:ic qu.i
Idnh

-;c
\;ic
ch)ng
V;IO
c.ie ht)p elen
do
tv
ben ngoi:li. Cae d.ip
ung
Cll.1
hl)p
den
SC
(ll1h
hU'l'mg
de'll
dlrCil1g
tin hieu
fa.
Cic
tin hieu c{l Cll
phci.p
k.hai
b.io nhu' sau.
signal
Ikcp: BIT:= '0';
signal
Res:
INTEGER
range

tLr0ng
pi1(fe
t' lp
han.
154
KiC;u
ph<.ll
du\1C
khai h,ia tmoe khi
Slr
dl.lOg.
Khai
h<to
kie'u
x<tc
c1inh
t(:11
kitu
vi\
mi6n x,\c
dinh
eua kieu. Cae khai baa kicu
e6
the
n:111l
troug
plHin
khai
b{lo
cLla

du'CJe
djnh nghia tru6c eua VHDL
Kicu
lm'tng
K ieu
h,in
ghi
Ki~u
STD_LOGIC.
SIGNED
va
UNSIGNED.
Ck
h~u
con.
a. Kicu
Ij~t
kc
Kieu li¢t ke dmJe
dPlh
nghia hilllg c{IC!1 li¢t
ke
t[{1
Cli
cae
gia !rj
e{)
the
e6
clla kicu.

co
(h~le
diem kh;ie
\,{1i
kieu
li('\
k0
eLlil
de
ngon ngiJ
1(lp
trlnh khae.
M{)i
gi,i
tri
trong
thimh ph[in ella
kicu
e6 tile
xuii! hi¢n
trong
hai
ho~\C
nhicu
hon kicu li¢t
kt.
Vi
d~l,
type
Color is (Red, Orange,

e .
~.
ch(Ta
nhCfng
phan
\\i
gi6ng nhall. Trong
VI
dl,l
tren, tmng
cac
ng6n ngiJ
I,)p
1:')5