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PHҪNIII
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BҦO Vӊ VÀ TӴ ĈӜNG HÓA
TRONG Hӊ THӔNG ĈIӊN
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Paper
An Improved Control Strategy for Hybrid Series Active Filter
dealing with Unbalanced Load
Nguyen Xuan Tung
∗
Non-member
Goro Fujita
∗
Member
Kazuhiro Horikoshi
∗∗
Member
This paper presents an improved control strategy for hybrid series active power filter (HSAF) working
with nonlinear and unbalance three-phase three-wire loads. An algorithm based on the Instantaneous Power

various series hybrid active power filter topologies re-
ported in literature
(4)∼(6)
, but the most common one is
shown in Fig. 1
Figure 1 shows the system configuration of series hy-
brid active power filter (APF), in which the shunt pas-
sive filter consists of one or more single-tuned LC fil-
ters and/or a high pass filter (HPF). The hybrid se-
ries APF is controlled to act as a harmonic isolator be-
tween the source and nonlinear load by injection of a
∗
Shibaura Institute of Technology
3-7-5, Toyosu, Koto-ku, Tokyo 135-8548
∗∗
Tohoku Electric Power Co.,Inc.
7-2-1, Nakayama, Aoba-ku, Sendai, Miyagi 981-0952
Fig. 1. Typical system configuration of hybrid se-
ries active power filter
controlled harmonic voltage source. It is controlled to
offer zero impedance at the fundamental frequency and
high impedance (ideally open circuit) at all undesired
harmonic frequencies. This forces all harmonic load cur-
rents to flow into the passive filter and decoupling the
source and nonlinear load at all frequencies, except at
the fundamental.
Control algorithm of the series active power filter
is mostly based on the Instantaneous Power Theory
(7)∼(10)
or the Synchronous Reference Frame (so-called

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the same frequency with that of the harmonic current
component as shown below:
[v
F
]=K ×[i
h
] ····························· (2)
with K is the amplification factor.
The performance of the active power filter depends
mainly on the selected reference generation scheme. The
reference current must reflex the desired compensation
current, however, since the Eq. 1 is used, certainly the
“harmonic” component here comprises all other current
components those differ from fundamental positive se-
quence current. Therefore this extraction method gives
the true harmonic component if the load is assumed to
be perfectly balanced.
In a quite common situation, the load current is usually
unbalanced with the existence of fundamental negative
sequence current. Consequently, that negative sequence
current will present in the extracted harmonic compo-
nent i
h
if Eq. 1 is still utilized although it is not a real
“harmonic” component. In this case, the series active
filter would have to handle not only the real harmonic
current but also the undesirable fundamental negative

lized for control system of active filter. Control strategy
based on this method provides fast response to changes
in power system, good compensating performance and
imposes a little computational burden
(17) (18)
.
Figure 2 shows the calculation block of this theory:
Firstly, three-phase voltages and load currents are trans-
formed into the stationary α-β reference frame (Clarke
transformation):

v
α
v
β

=

2
3
×

1 −1/2 −1/2
0
√
3

2 −
√
3

0
√
3

2 −
√
3

2

×
⎡
⎣
i
a
i
b
i
c
⎤
⎦
(4)
Next, the instantaneous real power p and instantaneous
reactive power q are calculated by:

p
q

=


˜p,˜q can be extracted from p, q and then the reference
harmonic current can be obtained as follow:

i
Fα
i
Fβ

=
1
v
2
α
+ v
2
β
×

v
α
v
β
v
β
−v
α

×

˜p

203
eBook for You
An Improved Control Strategy for Hybrid Series Active Filter dealing with Unbalanced Load
3. Approach for determining reference
current
3.1 Problem formulation and proposal All
the existing control strategies for the series active power
filter determine the reference currents i
h
by simply sub-
tracting the fundamental positive sequence current from
the supply current as below:
[i
h
]=[i
s
] −[i
fp
] ····························(8)
This approach has shown many disadvantages as already
mentioned in Sec. 1 since the reference current i
h
will
contain the fundamental negative sequence current com-
ponent if load is unbalanced. In order to overcome
this drawback, the improved reference current extrac-
tion method is proposed as follow:
[i
h
]=[i

•Generate an auxiliary voltage which contains only
a pure fundamental positive or negative sequence
voltage.
•This auxiliary voltage will be used together with ori-
gin supply current to create the instantaneous power
components.
•Implement filtering processes to achieve the desired
power portions from those power components then
applying inverse transformation to generate the cor-
responding current.
The role of the auxiliary voltage will be fully described
in next section.
3.2 Positive sequence current extraction Con-
sidering an auxiliary voltage that contains only funda-
mental positive sequence component
V
+1
with phase an-
gle φ
+1
assumed to be zero then the α-β transform of
this voltage results in:

v
+1α
=
√
3V
+1
sin (ω

+1
cos (−δ
+1
)
¯q

=3V
+1
I
+1
sin (−δ
+1
)
············(11)
here
•I
+1
: the fundamental positive sequence current
component of the measured supply current.
•δ
+1
: phase angle between the auxiliary positive se-
quence voltage V
+1
and the fundamental positive
sequence current component I
+1
.
It is clear to see that only fundamental positive sequence
voltage V

comes:

v
+1α
=+sin(ω
1
t)
v
+1β
= −cos (ω
1
t)
··················(12)
3.3 Negative sequence current extraction
Similar procedure is employed to extract negative se-
quence current, however, an auxiliary negative sequence
voltage is considered instead of the auxiliary positive se-
quence voltage.
Theresultsofα-β transform of this auxiliary pure fun-
damental negative sequence voltage is shown in Eq. 13.

v
−1α
=+sin(ω
1
t)
v
−1β
=+cos(ω
1

¯q

=3V
−1
I
−1
sin (−δ
−1
)
············(14)
here
•I
−1
: the fundamental negative sequence current
component of the measured supply current.
•δ
−1
: phase angle between the auxiliary negative se-
quence voltage V
−1
and the fundamental negative
sequence current component I
−
1
.
Again, only fundamental negative sequence voltage V
−1
and current I
−1
components show up in the average

1
t)and−cos(ω
1
t) those correspond to the
auxiliary fundamental positive sequence voltages v
+1α
& v
+1β
(mentioned in Eq. 12). The PLL circuit is al-
ready well introduced in literature and it has good per-
formance in handling this task
(19) (20)
(see Appendix for
operation principle).
Figure 3 shows the positive sequence detection circuit
based on principle stated in Sec. 3.2. Similar circuit can
be implemented for the negative sequence extraction if
the output of PLL circuit are −sin(ω
1
t) and cos(ω
1
t)
following the Eq. 13.
4.
Control strategy
4.1 Operation principle of series active filter
as harmonic current isolator It is well known
that series active filters correct current system distor-
tion caused by non-linear load by synthesizing an active
impedance presenting a zero impedance at fundamen-

I
sh
=
V
sh
Z
S
+ Z
F
+ K
+
Z
F
Z
S
+ Z
F
+ K
× I
h
··(15)
Fig. 4. Equivalent circuit for harmonic compensation
Fig. 5. Proposed control circuit for series active
filter
If the gain factor K is set sufficiently large as
K  (Z
S
+ Z
F
) then neither harmonic current flow

system then zero sequence component does not ex-
ist.
•Source’s line to line voltage is 200V (50Hz). Source
impedance is Z
s
=0.02∠80 pu (with the system
base of U
base
= 200V and S
base
=20kV A).
•Active filter rating capacity is 700VA and it is ac-
tivated at 0.5 [s] during simulation.
•PWM converter’s switching frequency is set at
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An Improved Control Strategy for Hybrid Series Active Filter dealing with Unbalanced Load
Fig. 6. Representative diagram for simulation
Table 1. Parameter of shunt passive filter
Inductance [mH] Capacitance [μF]
5
th
filter 1.2 340 Q=14
7
th
filter 1.2 170 Q=14
High-pass 0.26 300 R=3Ω

Result and discussion
6.1 Effectiveness of series active filter equipped
with improved control algorithm Figure 7 gen-
erally shows the effect of active power filter equipped
with improved control strategy on the nonlinear and un-
balanced load. For detail:
•Figure 7a shows that: Once active filter is acti-
vated at 0.5 [s] then it almost immediately takes ef-
fect to reduce the harmonic contents injecting into
the source, the source current almost becomes si-
nusoidal. Moreover, the active filter not only suc-
cessfully mitigates the harmonic contents but also
preserves perfectly the imbalance characteristic of
load as expected.
•Figure 7b & 7c present the spectra of source current
before and after active filter is activated. Evidently,
the harmonic contents significantly drops at all har-
monic frequencies. Thus, this is again to numer-
ically confirm the effectiveness of the series active
filter.
The fundamental positive and negative sequence cur-
rents extracted from measured source current are also
shown in Fig. 8 & Fig. 9. Noticeably, the positive and
negative sequence current remain constant, even while
active filter is operating. These results confirm the ad-
vantage of improved control strategy: the active filter
does not alter the load imbalance characteristic. In other
words, the active filter does work with only harmonic
0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560
-150

-150
-100
-50
0
50
100
150
Iap Ibp Icp
Fig. 8. Extracted positive sequence current
0.460 0.480 0.500 0.520 0.540 0.560
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
Ian Ibn Icn
Fig. 9. Extracted negative sequence current
current components as designed.
For nonlinear and balanced load, the active filter
equipped with new control strategy still works very well
as it can be seen in Fig. 10, the harmonic contents are
mostly eliminated and the inherent load characteristic
remains untouched.
6.2 Effectiveness comparison over series active
filters equipped with improved and previous con-
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150
Isa Isb Isc
(b) Result with previous control strategy
Fig. 11. Waveshape comparison in cases with im-
proved and previous control strategies
trol algorithms For comparison purpose, the active
filter which is equipped with the previous control strat-
egy is also simulated. Simulation studies for comparison
are setup based on follow assumptions:
•In previous control strategy, the negative sequence
component is not excluded from the reference har-
monic current.
•On the contrary, for the improved control strategy,
the negative sequence component is excluded from
the reference harmonic current.
•Comparisons are carried out with unbalanced loads
since the improved control strategy is proposed to
help the series active filter performs better under
unbalanced loading conditions.
•All other conditions remains the same for both
cases.
Figure 11 & 12 compare the current waveshapes and
spectra in cases the active filters utilize the improved
and previous control strategies. Under the same test-
ing conditions, the active filter with improved control
strategy shows a better performance. This conclusion
can be clarified in below discussion:
•The active filter equipped with previous control
strategy will have to handle both harmonic and the
fundamental negative sequence current components,

for harmonic mitigation function. As a result, the
harmonic mitigation efficiency in this case is higher.
This higher efficiency is illustrated in Fig.12a as the
harmonic contents shown there are much more lower
than those in Fig.12b. In other words, the active fil-
ter with the improve control algorithm has a better
performance.
Figure 13 shows the compensating voltages generated
by the series active filters (the blue and red lines show
instantaneous and RMS values respectively), those fig-
ures are for the output volt-ampere comparison purpose.
Figure 13b presents the output voltage of series active
filter which is equipped with previous control algorithm.
Apparently, looking at voltage waveform, one may see
the presence of the 50Hz component. That is reason
why the output voltage in RMS value is almost double
of that in Fig. 13a. This phenomenon is due to all the
previous control algorithms do not exclude the negative
sequence component which may occur if load is unbal-
anced.
For numerical detail comparison:
•In case the active filter employs improved control al-
gorithm, the compensating voltage presents a RMS
value of only about 3.4V . This means that the
volt-ampere rating of the series active filter is only
3.4V ×60A×3 = 612VA. Assuming that the active
filter rating capacity is chosen as 700VA, then this
figure presents only a small portion as about 3.5%
of the load rating 20kV A.
•On the contrary, if the previous control algorithm

12.0
16.0
20.0
V_active_filter VfilterRMS
(b) With previous control strategy
Fig. 13. Voltage generated by series active filters
Zs = 0.02
p
u
THDv (%)
1.06281
02
(a) Z
s
=0.02pu
Zs = 0.1
p
u
THDv (%)
2.01309
02
(b) Z
s
=0.1pu
Zs = 0.2
p
u
THDv (%)
2.30476
02

tortion.
Figure 15 show the corresponding THDs of source cur-
rents after compensation. Noticeably, after series active
filter was started, the remain amounts of harmonic con-
Zs = 0.02
p
u
THDi (%)
0.869893
02
(a) Z
s
=0.02pu
Zs = 0.1
p
u
THDi (%)
0.631617
02
(b) Z
s
=0.1pu
Zs = 0.2
p
u
THDi (%)
0.497768
02
(c) Z
s

component as expected, even when load is unbal-
anced.
•The proposed control strategy enhances the stabil-
ity of control process since the imbalance of load will
not have any affect on the reference signal.
•Especially, the active filter is protected away from
severer overload conditions because it does not have
to deal with the fundamental negative sequence
component which may occur if load is unbalanced.
•The proposed control strategy is well tailored to suit
with all operating conditions such as serving bal-
anced or unbalanced loads. In other words, it can
apply for the series active filter working with any
generic loads.
Finally, all the simulation results have successfully vali-
dated the effectiveness and feasibility of this proposal.
References
( 1 ) Z. Salam, and T. P. Cheng, and A. Jusoh, “Harmonics Miti-
gation Using Active Power Filter: A Technological Review”,
IEEJ Trans. TEEE, Vol.125, No.1, 2005 7
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208
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Elektrika Journal of Electrical Engineering, (2006)
( 2 ) F. Z. Peng, and H. Akagi, and A. Nabae, “A New Approach to
Harmonic Compensation in Power Systems”, IEEE Industry
Applications Society Annual Meeting, (1988)
( 3 ) M. El. Habrouk, and M. K. Darwish, and P. Mehta, “Active
Power Filters: A Review”, IEE Proceedings Electric Power

(12) G. D. Marques, and V. F. Pires, and M. Malinowski, and M.
Kazmierkowski, “An Improved Synchronous Reference Frame
Method for Active Filters”, The International Conference on
Computer as a Tool, (2007)
(13) S. Bhattacharya, and D. Divan, “Design and Implementation
of A Hybrid Series Active Filter System”, Power Electronics
Specialists Conference, (1995)
(14) K. Karthik, and J. E. Quaicoe, “Voltage Compensation and
Harmonic Suppression Using Series Active And Shunt Passive
Filters”, Canadian Conference on Electrical and Computer
Engineering, (2000)
(15) B. R. Lin, and B. R. Yang, and T. L. Hung, “Implementa-
tion of A Hybrid Series Active Filter for Harmonic Current
and Voltage Compensations”, International Conference on
Power Electronics, Machines and Drives, (2002)
(16) H. Akagi, and E. H. Watanabe, and M. Aredes: Instantaneous
Power Theory and Applications to Power Conditioning, John
Wiley & Sons, Inc. (2007)
(17) D. Chen, and S. Xie, “Review of The Control Strategies
Applied to Active Power Filters”, IEEE International Con-
ference on Electric Utility Deregulation, Restructuring and
Power Technologies, (2004)
(18) G. W. .Chang, and T. C. Shee, “A Comparative Study of
Active Power Filter Reference Compensation Approaches”,
Power Engineering Society Summer Meeting, (2002)
(19) S. A. O. Silvia, and P. F. Donoso-Garcia, and P. F. Seixas,
“A Three Phase Line Interactive UPS System Implementation
with Series-Parallel Active Power Line Conditioning Capaci-
ties”, IEEE Transactions on Industry Applications, (2002)
(20) F. F. Ewald, and M. A. S. Masoum: Power Quality in Power

b
+ v
c
i

c
= v
ab
i

a
+ v
cb
i

c
=¯p

3Φ
+˜p

3Φ
(A1)
The current feedback signals i
a
(ωt)=sin(ωt)and
i
c
(ωt)=sin(ωt + 120
0


3Φ
=3V
+1
I

+1
cos(φ
+
+ δ
+
) ··············· (A2)
where φ
+
and δ
+
are the initial phase angles of the fun-
damental positive sequence voltage and current i
a
(ωt)
respectively. Now the PLL can reach stable point of op-
eration only if the input p

3Φ
of PI controller has a zero
average value, that is equivalent to:
¯p

3Φ
=3V

v
+1a
= sin(ωt −90
0
) is in phase with fundamental pos-
itive sequence voltage V
+1
. Similar relations hold for
v
+1b
and v
+1c
.
Nguyen Xuan Tung (Non-member) received the B.E. de-
gree in electrical engineering from Hanoi Uni-
versity of Technology, VietNam in 1999 and
the M.E degree from Curtin University of
Technology, Australia in 2005. He has been
pursuing PhD degree in Shibaura Institute of
Technology, Japan since 2007. His interests
are about protective relay system and power
quality issue in power distribution system.
8 IEEJ Trans. TEEE, Vol.125, No.1, 2005
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An Improved Control Strategy for Hybrid Series Active Filter dealing with Unbalanced Load
Goro Fujita (Member) received the B.E., M.E. and Ph.D
degrees in electrical engineering from Hosei

Non-member
Fujita Goro
∗
Member
Dynamic Voltage Restorer (DVR) is a series custom compensator utilized in power distribution network,
however, due to connected in series with distribution line then DVR would suffer from downstream faults.
To limit the flow of large fault currents and protect DVR itself as well, a fault current limiting function is
proposed in the DVR control strategy. Fault current limiting function of DVR will be activated by protection
system and then DVR will start injecting a series voltage to the line in such a way to limit fault current
to an appropriate level (in accordance with required sensitivity of protection systems). The contribution of
this proposal is the utilization of signals from existing feeder protection system to activate DVR. This will
simplify the structure of DVR because the extra build-in fault detection module is not required. Moreover,
it will ensure proper coordination between DVR and protection systems.
Keywords: Dynamic Voltage Restorer, Fault Current Limiter, Protection System.
1. Introduction
Distribution networks are usually expanded by adding
either extra transformers and/or feeders. This fact may
raise the chances of increasing prospective fault currents
that might exceed circuit breaker’s interrupting capac-
ity. Moreover, that adding dispersed power sources may
be convinced as other reason for increasing potential
fault current level. Many solutions have been proposed
to deal with high fault duty level; one of these solutions
is utilizing fault current limiting (FCL) devices. Basi-
cally, FCL can bring many benefits to utilities, such as:
• Avoid or delay upgrading existing CBs.
• Minimize voltage dip on upstream bus when fault
occurs at downstream feeder.
• A larger transformer can be used to meet demand
without upgrading CBs.

with the above mentioned problems, a fault current lim-
iting function is added to DVR’s control function. When
fault occurs, the DVR reverses its injecting voltage po-
larity in such a way to pull down the current flow to an
appropriate level as desired. The advantages of added
fault current limiting function are:
• Additional protection circuits (such bypass circuit)
are not necessary for DVR.
• Implementation is simple.
• Diminish damage caused by large fault current to
circuit breaker and other equipment.
The fault current limiting function ensures that the de-
vices are protected from excessive high current without
additional circuit complexity. However, another concern
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Fig. 2. Equivalent diagram of investigated system
Fig. 3. Relationship between fault current and
voltage drop on fault impedance
is that the fault current limiting function of DVR must
not interfere with the existing protection system of the
feeder. Since the proposed function of DVR will force
the fault current to go down during the fault, in order
to avoid the interference it should be well coordinated
with the protection system.
In next section, the implementation of fault current
limiting function with activating signal from existing

X
f
=ΔU ················· (1)
where
U
S
: source voltage (behind source’s impedance)
Z
f
: total fault impedance (Z
f
= Z
S
+ Z
Lfault
)
I
f
: fault current
Z
S
: internal impedance of source
Z
Lfault
: impedance of faulty line section
ΔU: voltage drop on total fault impedance
If DVR is activated, it will inject a series voltage into
line in such a way to reduce amplitude of fault current.
At this time, relationship as shown in Eq. 1 has been
Fig. 4. Relationship between compensated fault

is kept in phase with pre-compensated fault current
I
f
then the amplitude of injected voltage is minimum
(U
DV R1
<U
DV R2
; U
DV R1
<U
DV R3
), therefore,
this technique minimizes the voltage rating of coupling
transformer (mathematical expression can be found in
ref. (3)), and hence, the voltage rating of DC capacitor
is minimized as well. In this proposal, in-phase current
compensation strategy is utilized.
3.
Activation and termination principles
implemented for DVR
Technical literature is filled with documents and ref-
erences regarding that utilizing the DVR as fault cur-
rent limiter , however, the coordination between DVR
and existing protection system has not been well men-
tioned
(4) (5) (6)
. Apparently, DVR will alter fault current
since it is activated, therefore, sensitivity of protection
system will be influenced. In order to ensure proper op-

large fault currents. Other concern is that some type of
protection system such as an overcurrent relay system
(non-directional type) will operate based on magnitude
of sensed current, hence if the fault current is compen-
sated to pre-fault level then overcurrent relay might no
longer have enough sensitivity to continue tracing the
presence of fault and it will reset to standby status.
Based on that analysis, a new setting level will be pro-
posed to ensure that protection system still functions
properly since DVR operates.
In order to deal with new setting level, the concept of
sensitivity of protection system will be referred
(7) (8) (9)
.
Generally, the protection system must operate reliably
even with the smallest fault current which may occur in
protective zone. However, what could happen in case
the smallest fault current is just about the setting level
(or pickup level) of protection system:
• If protection system still can operate in this case
that means it already senses the faulty condition or
it is sensitive enough.
• If it can not operate, that means the protection does
not sense the faulty condition, in other word, it is
not sensitive enough.
Based on that fact, the relationship between minimum
fault current and pickup level of any protection system
should be considered. In case of overcurrent relay, the
ratio between minimum fault current and setting level
is referred as the sensitivity factor of protection system

ensured.
3.2 Activation mechanism Normally, DVR is
used as multi-function device dealing with improvement
of power quality, for example, DVR may be utilized to
compensate for voltage sags, unbalanced voltage prob-
lems and harmonic compensations. However, when a
fault occurs somewhere downstream then a control sig-
Fig. 5. Activation mechanism applying for DVR
nal will be fed to DVR’s control circuit and DVR starts
working as fault current limiter. This control signal will
override all other control signals referred to above power
quality improvement functions.
I. Axente et al. proposed fault detection method by
adding an extra fault detection block
(4)
, this block took
responsibility for impedance measurement such that im-
plemented in commercial distance relays. However,
that adding extra impedance measurement block is very
costly solution (for reference, distance relay usually is
one of the most expensive relay) and the implementa-
tion of that block is not simple.
Other authors suggested a solution by adding over-
current detection block into DVR configuration
(6)
, but
building an extra block means that more money is
needed.
Besides those costly solutions, a simpler solution can
be implemented by extracting signal from existing pro-

Alternative solution to terminate DVR’s action pro-
posed in this study is based on the fact that: if com-
pensated fault current level is kept at 2 × I
pickup
(as
stated in Sect. 3.1), consequently when fault occurs, re-
lays will operate as normal even DVR is compensating
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Fig. 6. Termination mechanism applying for DVR
Fig. 7. Fault at load side and corresponding se-
quence actions
the fault current. Relay will count down setting time
and send tripping signal to open CB whenever setting
time is over. At the moment when relay issues tripping
signal, DVR should be terminated.
Based on that analysis, termination signal feeding to
DVR can be extracted from tripping circuit of relay.
This principle is illustrated in Fig. 6.
In case of fault occur at load side as shown in Fig. 7,
both protection systems of load and feeder pick up, but
only load’s protection system (LPS) trips and open CB
at load side. Whenever fault is cleared by opening CB at
load side, feeder’s protection (FPS) will reset to standby.
In this situation, DVR already is activated due to FPS
picked up, but there is no signal to terminate DVR’s op-
eration since FPS reset without issuing any tripping sig-

prot
···························· (3)
where:
P
c
: total active power flowing into DVR.
t
prot
: operating time of protection system.
Total active power P
c
flowing into DVR is determined
by:
P
c
=3× V
injected
× I
compensated
× cos(θ) ···· (4)
with θ = angle(V
injected
,I
compensated
)
Maximum voltage can occur across capacitor is:
U
DCmax
=


• If only DC-link voltage monitoring mechanism
is utilized: basically, DC-link voltage monitoring
mechanism takes time to process signal and it will
not respond as fast as FPS does in case of fault oc-
curs at feeder. In other word, DC-link voltage mon-
itoring mechanism will give a bit longer fault clear-
ance time in comparison with that done by FPS.
4.
Circuit and control block of DVR serv-
ing as fautl current limiter
Simulation was implemented by PSCAD software.
The proposed DVR model is three phase inverter model
with common DC energy storage as shown in Fig. 9.
Main components of DVR model include:
• Coupling transformer.
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Fault Current Limiting Function of Dynamic Voltage Restorer Utilizing Signals from Existing Protective Relays
g11
g21
g31
g42
g52
g62
1
2
3

2
g12
g41
1
2
4
2
Vsa
Vsb
Vsc
Vasend
Vbsend
Vcsend
Iasend
Ibsend
Icsend
1.0
A
B
C
VFPh
FAUL TS
C
B
A
Fault Type
C
B
A
BK

Icref
Ibref
Iaref
120.0
120.0
*
*
*
*
1
D
+
F
-
Delta_
a
Delta_
b
Delta_
c
Ia
Ib
Ic
Ma
g
. of referece current
D
+
F
-

current is compared with the reference currents, and
the difference is fed through PI controller to generate
a modulation index which is applied to the pulse width
modulated (PWM) carrier switching signal to generate
turn-on and turn-off pulses to the IGBTs. The control is
single phase based to achieve best performance, in other
word; the DVR has independent phase control.
For fast response and to maximize dynamic perfor-
mance, direct feed-forward type control architecture is
Fig. 11. Control principle used to keep DVR in
null state
applied in the control strategy of the DVR. With this
control, a fast response time (approximately half cycle)
can be achieved to compensate fault currents.
During normal condition, DVR is kept in null state.
This state is implemented by removing the PWM firing
from the IGBTs in the phases and instead, continuously
fires the IGBTs in half of each single phase portion of
the VSI as shown in Fig. 11, so that the series wind-
ings are short circuited. When DVR is activated, PWM
firing is fed to all IGBTs in phases as normal.
5.
Simulation and discussion
5.1 Simulation setting In this study, simula-
tions were run with following parameters:
• Maximum load current: I
Loadmax
 75 [A]
• Maximum fault current: I
F aultmax

0.000 0.050 0.100 0.150 0.200 0.250 0.300
-1.0k
-0.8k
-0.5k
-0.3k
0.0
0.3k
0.5k
0.8k
1.0k
y
Ia Ib Ic
Fig. 12. Three-phase fault without DVR
CURRENT
(
in Am
p
ere
)
0.000 0.050 0.100 0.150 0.200 0.250 0.300
-1.0k
-0.8k
-0.5k
-0.3k

5.3 Result and discussion Simulation results
and discussion are shown below.
Figure 12 shows three-phase fault current (fault takes
place at feeder) with DVR is not activated, fault cur-
rent is about 700 [A] (about ten times of normal load
current). In case DVR is activated (Fig. 13), DVR
takes full effect just after one cycle and fault current is
reduced to 230 [A] (rms) as expected. In this case, DVR
is activated and terminated by FPS.
Comparing Fig.12 with Fig. 13, it can be seen that
the operation of FPS is not interfered even while DVR
is operating, FPS cleared fault after 0.2 [s] based on its
own setting. Similarly, Fig. 14 and Fig. 15 show the
case of phase-phase fault.
In Fig. 15, it can be seen that, DVR performed sin-
gle phase control perfectly, only two faulty phases (a
and b) are compensated while healthy phase (c) remain
constant. Moreover, fault clearance time of relay still
CURRENT
(
in Am
p
ere
)
0.000 0.050 0.100 0.150 0.200 0.250 0.300
-1.0k
-0.8k

Ia Ib Ic
Fig. 15. Phase-phase fault with DVR activated
CURRENT
(
in Am
p
ere
)
0.000 0.050 0.100 0.150 0.200 0.250 0.300
-1.0k
-0.8k
-0.5k
-0.3k
0.0
0.3k
0.5k
0.8k
1.0k
y
Ia Ib Ic
Fig. 16. Three-phase fault at load side without
DVR
is 0.2 [s] that means DVR’ operation did not affect the
protection system.
In next section, the cases with three-phase fault at
load side (as shown in Fig. 7) is investigated. Firstly,
DVR is not activated. In this situation, fault current is

)
0.000 0.050 0.100 0.150 0.200 0.250 0.300
-1.0k
-0.8k
-0.5k
-0.3k
0.0
0.3k
0.5k
0.8k
1.0k
y
Ia Ib Ic
Fig. 17. Three-phase fault at load side with DVR
activated by FPS and terminated by DC-link volt-
age tracing mechanism
Main : Gra
p
hs
0.000 0.050 0.100 0.150 0.200 0.250 0.300

-2.0
0.0
2.0
4.0
6.0
8.0

ence with an inverter-based dynamic voltage restorer”, IEEE
Transactions on Power Delivery, Vol. 14, No.03, pp.1181–
1186
( 3 ) G. Xiao, Z. Hu, C. Nan, and Z. Wang, “DC-Link voltage
pumping-up analysis and phase shift control for a series active
voltage regulator”, Proceeding of 37th IEEE Power Electron-
ics Specialists Conference, pp.1–5 (2006)
( 4 ) I. Axente, M. Basu, M. F. Conlon,, and K. Gaughan, “Protec-
tion of DVR against short circuit faults at the load side”, Pro-
ceeding of the 3rd IET International Conference on Power
Electronics, Machines and Drives, pp.627–631 (2006)
( 5 ) S. S. Choi, T. X. Wang, and D. M. Vilathgamuwa, “A se-
ries compensator with fault current limiting function”, IEEE
Transactions on Power Delivery, Vol. 20, No.03, pp.2248–
2256
( 6 ) L. Y. Wei, D. M. Vilathgamuwa, C. L. Poh, and F. Blaab-
jerg, “A dual-functional medium voltage level DVR to limit
downstream fault currents”, IEEE Transactions on Power
Electronics, Vol. 22, No.04, pp.1330–1340
(7) GET-6450 Distribution System Feeder Overcurrent Protec-
tion, GE Publication (1997)
(8) IEEE Std. 1596-1992,Guide for Protective Relay Applica-
tions to Transmission Lines, IEEE (1992)
( 9 ) A. C. Enriquez and E. V. Martinez, “Sensitivity improve-
ment of time overcurrent relays”, Electric Power Systems Re-
search, Vol. 77, No.02, pp.119–124 (2007)
Appendix
Parameters in simulation
- Source & Load (Fig. 9)
Source voltage: 7.5 [kV] (L-L, RMS)

nology, VietNam in 1999 and the M.E degree
from Curtin University of Technology, Aus-
tralia in 2005. Currently, he has been pursuing
PhD degree in Shibaura Institute of Technol-
ogy, Japan. His interests are about relay pro-
tection system and power quality issue.
Fujita Goro (Member) was born in January 1970. He re-
ceived the B.E., M.E. and Ph.D degrees in
electrical engineering from Hosei University,
Tokyo, Japan in 1992, 1994 and 1997 respec-
tively. In 1997, he was a research student of
Tokyo Metropolitan University. Since 1998, he
is in Shibaura Institute of Technology, Tokyo,
Japan as an associate professor. His interest
is in power system opeartion and control. He
is a member of the Society of Instrument and
Control Engineers (SICE) of Japan, the IEE of Japan, and IEEE.
IEEJ Trans. TEEE, Vol.xxx, No.xx, xxxx
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Paper
Phase Load Balancing In Distribution Power System
Using Discrete Passive Compensator
Nguyen Xuan Tung
∗
Non-member
Goro Fujita

transposition of feeder lines.
The influence of imbalance voltage and current on
power system has been well investigated in literature.
V. J. Annette et al.
(1)
and L. F. Ochoa et al.
(2)
con-
cluded that unbalanced voltages and currents can result
in adverse effects on equipment and on the power sys-
tem, for example a small unbalance in the phase volt-
ages can cause a disproportionately larger unbalance in
the phase currents. Under unbalanced conditions, the
power system will incur more losses and heating effects.
The effect of voltage unbalance can also be severe on
equipment such as induction motors, power electronic
converters and adjustable speed drives.
Many mitigation techniques have been developed to
deal with imbalance phenomenon in distribution system,
generally those solutions can be divided into two cate-
∗
Shibaura Institute of Technology
3-7-5, Toyosu, Koto-ku, Tokyo 135-8548
∗∗
Tohoku Electric Power Co.,Inc.
7-2-1, Nakayama, Aoba-ku, Sendai, Miyagi 981-0952
gories:
• Rearrange feeders or redistribute the loads in such a
way the system becomes more balanced
(3)∼(5)

that minimize the unbalanced power flow through the
main feeder. The algorithm allows the user to specific
the type and the maximum number of available taps
for each compensator. In addition, detailed model of
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Fig. 1. Diagram of unbalanced load and compensator
the feeder including mutual coupling effect, the type of
loads and time-varying load patterns are also considered
in the algorithm in order to suggest the compensator’s
switching patterns over time. Finally, the algorithm is
written in MATLAB language and tested on the data
retrieved from an actual three-phase, three-wire distri-
bution feeder to verify its effectiveness.
2.
Compensation principle
Figure 1 shows the general unbalanced three-phase
load fed from a three-phase, three-wire source. Load
and compensator are connected in delta therefore zero
sequence component will equal to zero. The compen-
sator currents (
.
I
ac
,
.
I

ac
=(
.
I
a1l
+
.
I
a2l
+
.
I
a0l
)+(
.
I
a1c
+
.
I
a2c
+
.
I
a0c
)
=(
.
I
a1l

.
I
a1
,
.
I
a2
,
.
I
a0
: positive, negative and zero current
sequence components.
The objective of load compensation is to eliminate or
limit any the negative and zero sequence components of
load currents. Since zero components are zero therefore
in this case the line currents will become perfectly bal-
anced if the negative sequence component is eliminated.
Mathematic expression of above statement is shown in
Eq. 2
(
.
I
a2l
+
.
I
a2c
)=0···························· (2)
Because I

sator
One of the factors which electrical utility consider
Fig. 2. Diagram of three-phase compensator
when installing the compensator is the capital cost,
therefore the lossless compensator is a first top prior-
ity and the simplicity of compensator bank is preferred
as well. For those reasons, capacitive and inductive com-
pensator banks would be the most prominent solutions.
Furthermore, if a compensator consists of both inductive
and capacitive banks then the compensation system will
be obviously more complex than that if only either pure
capacitive or pure inductive bank is used. Moreover,
the higher complexity degree of compensator will result
in more investment money and more time for mainte-
nance. In order to offer cost advantages to utilities, the
possibility of using only either capacitive or inductive
compensation bank as the phase loading compensator
will be proven in this section.
Considering the general case where the compensator
is full thee-phase and delta connection as shown in Fig. 2
(here Y
ab
, Y
bc
, Y
ca
are compensator’s admittances).
Assume that phase voltages are perfectly balanced:
.
V

=

.
Y
ab
(1 − a
2
) −
.
Y
ca
(a − 1)

× V
.
I
bc
=

.
Y
bc
(a
2
− a) −
.
Y
ab
(1 − a
2

⎩
.
I
a0
=0
.
I
a1
=(
.
Y
ab
+
.
Y
bc
+
.
Y
ca
) × V
.
I
a2
= −(a
2
.
Y
ab
+

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Phase Load Balancing In Distribution Power System Using Discrete Passive Compensator
Fig. 3. Diagram of single-phase compensations
Table 1. Negative current components con-
tributed by various single phase compensator
configurations
Negative Current
Compensator
Capacitive Inductive
.
I
a2(AB)
1∠30
0
1∠−150
0
.
I
a2(BC)
1∠−90
0
1∠90
0
.
I
a2(CA)
1∠150

× V
···········(6)
Here subscript “AB” denotes current quantities re-
sulting from the single phase compensator con-
nected across phases A&B.
◦ If the compensator is capacitive element with
impedance of X
C
.
I
a2(AB)
= −a
2
×
.
Y
ab
× V
=
V
X
C
∠30
0
=1∠30
0
········ (7)
◦ If the compensator is inductive element with
impedance of X
L

Fig. 5. Decomposition of required negative cur-
rent vector into two nearest component vectors
magnitudes of a (pu) and b (pu) respectively as
shown in (Fig.5-a).
In order to generate the a (pu) vectors on CA axis
then a single phase capacitive compensator con-
nected across phases C&A must be used (accord-
ing to Table. 1). The value of CA capacitive single
phase compensator will be:
X
C(CA)
=
1
a
→ Y
ca
=
1
X
C(CA)
= a (pu)
Similarly, another single phase capacitive compen-
sator connected between phases B&C must be used
to generate b (pu) vector on BC axis.
X
C(BC)
=
1
b
→ Y

4.
Phase load balancing in distribution
system
4.1 Problem formulation The implementation
of load balancing or load compensation in distribution
level may involve some of follow aspects:
Technical aspects:
• Compensation algorithm must be able to apply to
calculate for not only individual load but also for
feeder with several connected loads. The problem
of unbalanced phase loading is not new in power
systems, however, the previous proposed solutions
are to deal with single individual unbalanced load
only and they did not figure out how to deal with
the feeder which has several connected loads
(6)∼(9)
.
The contribution of this paper is to propose an al-
gorithm which can apply to solve the unbalanced
phase loading phenomenon for not only single load
but also for the feeder accommodating several loads
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Fig. 6. Representative feeder
as seen in practice.
• Algorithm must produce as more accurate results
as possible in comparison with other proposed so-

to the fact that thermal inertias of equipments are quite
long. Based on that analysis, it is not really imperative
to instantly correct the imbalance phase loading situ-
ation since it occurs and the balancing action can be
carried out on averaged data over a time interval. In
other word, if daily loading curve is known then it can
be stripped into smaller intervals and the compensation
action will be calculated based on the unbalance factor
averaged over each that time interval.
From above view point, load balancing algorithm is pro-
posed as follow: Considering the representative feeder
with m loads as shown in Fig. 6.
Step 1: Determine the first loading level (n =1)toas-
sess for imbalance compensation (here n stand for load-
ing level order).
Step 2 : Run three-phase, unbalance power flow calcu-
lation with the given loading level from step 1.
This unbalance power flow module has ability to handle
for various types of loads such as the load with con-
stant power; load with constant impedance or load with
constant current
(11)
. Furthermore, mutual impedance of
distribution line is also taken into account.
The outputs of this step will be all node voltages
(V
Ai
,V
Bi
,V

1
3
(
.
I
ali
+ a
2
.
I
bli
+ a
.
I
cli
)
= C
i
+ jD
i
·····························(9)
with C
i
and D
i
are real and imaginary parts of negative
current produced by load number i.
Step 4 : Calculate the compensator size. This step
consists of the follow sub-steps:
* Establish load balancing equations to determine the

− (
.
V
Ci
−
.
V
Ai
)
.
Y
cai
.
I
bci
=(
.
V
Bi
−
.
V
Ci
)
.
Y
bci
− (
.
V

V
Ci
)
.
Y
bci
(10)
Here Eq. 10 looks different with Eq. 4 due to the fact
that actual voltages
.
V
Ai
,
.
V
Bi
,
.
V
Ci
of node i are used
instead of assumed balanced voltages V . In Eq. 10, node
volatges
.
V
Ai
,
.
V
Bi

+ a
2
.
I
bci
+ a
.
I
cci
)
= E
i
+ jF
i
··························· (11)
here E
i
and F
i
are real and imaginary parts of negative
current required to generate by compensator number i.
Note that E
i
and F
i
are functions of variables
.
Y
abi
,

(
.
Y
abi
,
.
Y
bci
,
.
Y
cai
)
Load balancing process is to satisfy the balancing con-
ditions as stated in Eq. 3, in this context, substitute
E
i
,F
i
,C
i
,D
i
into Eq. 3 we come up with following load
balancing equations:

E
i
(
.

··········· (12)
Or in general form

E
i
(Y )+C
i
=0
F
i
(Y )+D
i
=0
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Phase Load Balancing In Distribution Power System Using Discrete Passive Compensator
with Y represents for compensator’s admittance.
* Solve load balancing equations by utilizing discrete
optimization technique.
Since load balancing conditions or equations have been
already established in Eq. 12 then the target of this step
is to find out the values of variables Y
abi
, Y
bci
, Y
cai

with E
i
& F
i
are function of compensator’s admit-
tance Y .
subject to
⎧
⎨
⎩
Y : set of n
d
discrete values

[Y ]
n
d
≥ [0] (for capacitor)
[Y ]
n
d
≤ [0] (for reactor)
n
d
: maximum number of taps for each compensator.
Each element of [Y ]
n
d
will be assigned to a value of cor-
responding tap in a discrete manner.

sponding loads then it is necessary to check for any fur-
ther compensation correction. This can be done by going
back to step 2 to run power flow again with all updated
loads and repeat all the above mentioned procedures.
The iteration will terminate whenever no further com-
pensation correction is required.
The condition to terminate calculation process is as fol-
low:
Whenever the conditions Y
abi
= Y
bci
= Y
cai
with all
i =1÷ m are satisfied then the iteration will stop be-
cause those conditions mention that all compensators
now are three-phase balanced. Since they are balanced
they will not produce any negative current to cancel for
load negative current. In other word, at this stage the
compensator size is already an optimal value and no fur-
ther compensation is needed.
Fig. 7. Phase load balancing algorithm
Outputs of this step 6 will be the final values of all
compensators. Those discrete optimal compensator’s
sizes will be used to determine the corresponding tap
positions. Those tap positions are the first switching
patterns of the compensators corresponding to the first
loading level.
Since compensation strategy to deal with a certain

10
12
14
16
Time Interval
Percentage (%)
Negative current through Line 1
Before After
Fig. 9. Negative currents before & after compen-
sation through Line 1
pacitive compensators are used then the power fac-
tor will become worse.
• Compensators are switchable with maximum 10
steps and each step is 25kVAR; 15kVAR and 5
kVAR for compensator 1; compensator 2 and com-
pensator 3 respectively.
In this paper, time interval for unbalance assessment is
selected as 2 hours, in other word, each compensator will
have 12 time-switching patterns over every 24 hours or
aday.
The load balancing algorithm is written in MATLAB.
This algorithm consists of two main modules.
• The first is unbalance power flow module. This un-
balance power flow module has ability to handle for
various types of loads such as the load with constant
power; load with constant impedance or load with
constant current. Furthermore, mutual impedance
of distribution line is also taken into account
(11)
.

12
14
16
Time Interval
Percentage (%)
Negative current through Line 2
Before After
Fig. 10. Negative currents before & after compen-
sation through Line 2
1 2 3 4 5 6 7 8 9 10 11 12
0
10
20
30
40
50
Time Interval
Percentage (%)
Negative current through Line 3
Before After
Fig. 11. Negative currents before & after compen-
sation through Line 3
1 2 3 4 5 6 7 8 9 10 11 12
0
0.1
0.2
0.3
0.4
0.5
0.6

Figure 15, 16 and 17 show the absolute value of node
voltages with respect to the source voltage of 6750 (V).
In this simulation, the downstream node voltages some-
times are higher than the source voltage due to the lead-
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Phase Load Balancing In Distribution Power System Using Discrete Passive Compensator
1 2 3 4 5 6 7 8 9 10 11 12
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Time Interval
Percentage (%)
Negative voltage at node 3
Before After
Fig. 14. Negative voltage before & after compen-
sation at node 3
1 2 3 4 5 6 7 8 9 10 11 12
5600
5800
6000

about ± 3 % and all node voltages are within allowable
level.
The switching patterns of compensators are indicated
by their tap positions versus time. The results are pre-
sented in Fig. 18, 19 and 20. Moreover, the compen-
sation shows not only load balancing effect but it also
helps to reduce power losses through the investigated
system. Figure 21 shows power loss improvement after
compensation.
In this context, the power losses improvement (PLI) is
defined as follow:
1 2 3 4 5 6 7 8 9 10 11 12
5600
5800
6000
6200
6400
6600
6800
7000
Time Interval
Node Voltage (V)
Phase A Phase B Phase C After
Fig. 17. Absolute voltage value before & after
compensation at node 3
1 2 3 4 5 6 7 8 9 10 11 12
0
50
100
150

50
60
Time Interval
Tap position (kVAR)
Tap position vs Time for Compensator 3
AB BC CA
Fig. 20. Tap position vs Time for Compensator 3
PLI =
PL
bf
− PL
af
PL
bf
× 100 (%)
where PL
bf
and PL
af
are total power losses before and
after compensation.
According to results of simulation, power losses im-
provement can be more than 70% and in the the least
remarkable situation it is about 16%. The possible rea-
sons for power losses improvement can be convinced as
follow:
• As stated in Ref. (2), under unbalance loading situa-
IEEJ Trans. TEEE, Vol.xxx, No.xx, xxxx 7
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