Process Variations and Probabilistic Integrated
Circuit Design

Manfred Dietrich • Joachim Haase
Editors
Process Variations and
Probabilistic Integrated
Circuit Design
123
Editors
Manfred Dietrich
Design Automation Division EAS
Fraunhofer-Institut Integrierte Schaltungen
Zeunerstr. 38, 01069 Dresden
Germany

Joachim Haase
Design Automation Division EAS
Fraunhofer-Institut Integrierte Schaltungen
Zeunerstr. 38, 01069 Dresden
Germany

ISBN 978-1-4419-6620-9 e-ISBN 978-1-4419-6621-6
DOI 10.1007/978-1-4419-6621-6
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2011940313
© Springer Science+Business Media, LLC 2012
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York,
NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in

next-generation
EDA technology and is currently oriented specifically at addressing timing
analysis and power sign-off. Research into this field commenced about five years
ago and saw significant activity during the period since that start, although there are
indications of reduced interest of late. This decline in activity may be partly due
to the fact that the results of the work have been slow to find application. Perhaps
the key direction identified during this period has been the need to develop and
optimize statistical models for integrated circuit library components, and it is in this
v
vi Preface
area that effort will probably concentrate in the near future. This book will present
some results from research into this area and demonstrate how the manufacturing
parameter variations impact the design flow.
On the one hand, it is the objective of this book to provide designers with a
qualitative understanding of how process variations influence circuit behavior and to
indicate the most dominant parameters. On the other hand, from a practical point of
view, it must also acknowledge that designers need appropriate tools and strategies
to evaluate process variants and extract the modeling parameters.
It is true that certain modeling methods have been employed over the years
and constitute the framework under which submicron integrated circuits have been
developed to date. These have concentrated on evaluating a myriad of electrical
model parameters and their variation. This has led to an accurate determination of
the inter-dependence of these parameters under given conditions and does provide
the circuit developer with certain design information. For example, the designer can
determine whether the leakage current of a given cell or circuit is greater than a key
threshold specification, and similar determinations of power and delay can be made.
In fact, this modeling approach can include many parameters of low order effect yet
can be defined in such a way that many may be easily monitored and optimized in
the fabrication technology.
However, this specific case and corner analysis cannot assess such key factors

problems that arise because of intrinsic parameter variations, illustrates the differ-
ences between the various methods used to address the variations, and indicates the
direction in which one must set course to find general solutions.
The core material for the book came from many sources – from consultation
with many experts in the semiconductor and EDA industries, from research centers,
and from university staff. It is only from such a wide canvas that the book could
genuinely represent the broad spectrum of views that surround this subject. The
heart of the book is thus that of these contributors, experts in the field who have
embodied their frustrations and practical experience in each page.
Certain chapters of the book use results obtained during two German re-
search projects which received funding from the German Federal Ministry of
Education and Research (BMBF). These projects are entitled ”Sigma 65: Tech-
nologiebasierte Modellierung und Analyseverfahren unter Bercksichtigung von
Streuungen im 65nm-Knoten” (Technology based modeling and analyzing meth-
ods considering variations within 65nm technology) and ”ENERGIE: Technolo-
gien fr energieeffiziente Computing-Plattformen”(Technologies for energy-efficient
computing platforms; the subproject is part of the the Leading-Edge Cluster
CoolSilicon)
1
. Both projects address technology nodes beyond 65nm.
All contributors would like to thank the Springer Publishing Company for giving
them the opportunity to write this book and have it published. Special thanks go
to our Editor, Charles Glaser, for his understanding, encouragement, and support
during the conception and composition of this book. We also thank very much
Elizabeth Dougherty and Pasupathy Rathika for their assistance, efforts and patience
during the preparation of the print version.
Last but not least, we cannot close without thanking also the management and
our colleagues at the Fraunhofer-Gesellschaft (Design Automation Division of the
Institute for Integrated Circuits) without whose support this book would not have
been possible. Being able to work within the infrastructure of that organization

Glossary 245
Index 247
ix

Acronyms
ACM Advanced Compact Model
ADC Analog-to-Digital Converter
ANOVA Analysis of variance
ASIC Application-specific integrated circuit
BSIM Berkley short-channel IGFET model
CCS Composite current source model
CD Critical Dimension
CDF Cumulative distribution function
CGF Cumulant generating function
CLM Channel length modulation
CMC Compact Model Council
CMCal Central moment calculation method
CMP Chemical-mechanical polishing
CMOS Complementary metal-oxide-semiconductor
CPF Common power format
CPK Process capability index
CSM Current source model
DAC Digital-to-Analog Converter
DCP Digital Controlled Potentiometer
DF Distribution function
DFM Design for manufacturability
DFY Design for yield
DIBL Drain-induced barrier lowering
DNL Differential Nonlinearity
DoE Design of Experiments

MSB Most Significant Bit
NBTI Negative bias temperature instability
NLDM Nonlinear Delay Model
NLPM Nonlinear Power Model
NQS Non-Quasi Static
OASIS Open Artwork System Interchange Standard
OPC Optical Proximity Correction
OCV On-chip variation
PCA Principal Component Analysis
PDF Probability density function
PDK Process Design Kit
POT Peak over threshold
PSP Penn-State Philips CMOS transistor model
PVT Process-Voltage-Temperature
RDF Random doping fluctuations
RSM Response Surface Method
SAE Society of Automotive Engineers
SAR Successive Approximation Register (ADC type)
SAIF Switching Activity Interchange Format
SDF Standard Delay Format
SOI Silicon on insulator
SPA Saddle point approximation
Acronyms xiii
SPE Surface Potential Equation
SPEF Standard Parasitic Exchange Format
SPDM Scalable Polynomial Delay Model
SPICE Simulation program with integrated circuit emphasis
STA Static timing analysis
STARC Semiconductor Technology Academic Research Center
SSTA Statistical static timing analysis

T
Thermal voltage k
B
T/q
I
ds
Drain-source current
I
gs
Gate-source current
V
dd
Supply voltage
V
gs
Gate-source voltage
V
ds
Drain-source voltage
V
sb
Source-bulk voltage
I
leak
Leakage current
I
GIDL
Gate-induced drain leakage current
I
sub

L
eff
Effective channel length
ε
F
Fermi level
k
B
Boltzmann constant
J
J
J Jacobian matrix
X Random variable X (one dimensional)
x Sample point of a one-dimensional random variable x
xv
xvi List of Mathematical Symbols
X Random vector X
x Sample point of a random vector x
Σ
Covariance matrix
Σ
N(
μ
,
σ
2
) Univariate normal distribution with mean value
μ
and
variance

limit
) Probability for X ≤ x
limit
ρ
X,Y
Correlation coefficient of random variables X and Y
Chapter 1
Introduction
Joachim Haase and Manfred Dietrich
During the last years, the field of microelectronics has been moving to nanoelec-
tronics. This development provides opportunities for new products and applications.
However, development is no longer possible by simply downscaling technical
parameters as used in the past. Approaching the physical and technological limits of
electronic devices, new effects appear and have to be considered in the design pro-
cess. Due to the extreme miniaturization in microelectronics, even small variations
in the manufacturing process may lead to parameter variations which can make a
circuit unusable. A new aspect for digital designers is the occurrence of essential
variations not only from die to die but also within a die. Therefore, inter-die and
intra-die variations have to be taken into account not only in the design of analog
circuits as already done, but also in the digital design process. The great challenge is
to assure the functionality of high complex digital circuits with respect to physical,
technological, and economic boundary conditions. In order to evaluate design
solutions within an acceptable time and with acceptable efforts the methods applied
in the design process must support the analysis of design solutions as accurate as
necessary and as simple as possible. As a result, the expected yield will be achieved
and circuits can be manufactured economically. In this context, CMOS technology
will remain the most important driving force for microelectronics over the next years
and will be responsible for most of the innovations and new applications. For this
reason, the subsequent paragraph will focus on this technology. The first chapter
provides an introduction to the outlined problems.

moving from one node
to the next. Over two cycles, the scaling factor is 0.5. In accordance with this devel-
opment, the device parameters, line parameters, and electrical operating conditions
were scaled. The result was a decrease of the delay time of digital components with
simultaneous decrease of the their sizes. Thus, faster chips with more components
could be developed that enabled a higher functionality. For more than 35 years, the
fundamental paper by Robert H. Dennard and others [2] could be used as a compass
for research and development in this area (see Tables 1.1 and 1.2,
α
=
√
2).
Fig. 1.1 2009 Definition of
pitches [1]
1 Introduction 3
Table 1.1 Scaling of device
parameters [2, 3]
Parameter Scaling factor
Channel length L 1/
α
Channel width W 1/
α
Oxide thickness t
ox
1/
α
Body doping concentration N
a
α
Threshold voltage V

Wire thickness t
w
1/
√
α
Line resistance R
L
∼
L
w
W
w
t
w
α
Line response time ∼R
L
C 1
Wire-to-wire capacitance ∼
κ
isolation
s
w
t
w
L
w
1
Table 1.3 Scaling for circuit
performance [2, 3]

Increasing with
α
The scaling rules assured not only the functional progress. Performance was
increased while reducing power per circuit components. The power density retained
stable (see Table 1.3).
However, for instance downscaling the threshold voltage V
th
and oxide thickness
t
ox
results in higher subthreshold leakage and gate leakage currents resp. [4]. Thus,
power consumption became more and more a problem. “Dennard’s Law” could no
longer be followed [5]. To overcome the limits, new materials, new devices, and
new design concepts have been investigated [6]. In parallel, process variations have
to be considered in order to predict performance and yield of VLSI designs.
Further trends include, on the one hand, geometrical and equivalent scaling and,
on the other hand, a functional diversification. The first trend is announced as “More
Moore” while the second is discussed as “More than Moore” [1]. At the end, system-
level performance has to be improved [7]. In order to compare different solutions,
reliable methods to predict the system behavior are becoming necessary.
4 J. Haase and M. Dietrich
1.2 Consequences of Silicon Technology Challenges
Reducing the channel length of the CMOS devices, short-channel effects such as
velocity saturation and drain-induced barrier lowering have to be considered. The
threshold voltage V
th
strongly depends on the effective channel length L
eff
and the
operational voltages. These and other effects have to be considered in the transistor

ox
β
1
,where
β
1
is a fitting coefficient.
The value strongly depends on the gate thickness t
ox
. The gate leakage results from
tunneling of electrons through the gate dielectric [8]. The gate capacitance must
be maintained over a limit while shrinking the geometry in order to assure the
controllability of the channel current. Thus, shrinking of the gate thickness could be
avoided by a gate material with high permittivity known as high-k material. “High”
notes that the permittivity is greater than that of silicon oxide SiO
2
.
Shrinking the geometry also influences the interconnection of components. The
delay of local wires between gates remains constant (see Table 1.2). However, global
wires such as busses and clock networks tend to follow the chip dimensions. Wires
can be considered as distributed RC lines. The delay depends on the product of line
resistance times line capacitance. Thus in order to reduce the delay, interconnect
materials with lower resistance and dielectrics with lower permittivity (low-k
materials) have been investigated. For instance, a lower resistance can be achieved
by using copper instead of aluminium for interconnect lines. A lower permittivity
reduces also the parasitic wire-to-wire capacitance. However, it is suspected that
modifications of the dielectric material could lead to an inacceptable leakage.
Looking at the RC product, it follows that the delay of the interconnect lines
increases quadratically with its length. Thus, splitting the long interconnect lines and
inserting repeaters is a reasonable strategy to reduce the overall delay [9]. However,

inter
+ P
intra
. (1.1)
Besides these variations, changes of the environment a circuit operates in must
also be considered. The temperature, supply voltages, and input signals have
an impact on the circuit performance. These variations are called environmental
variations. The functionality of a circuit must be guaranteed within specified limits.
Last but not least the functionality over time must be assured. Aging effects such
as electromigration and negative bias temperature instability are further sources of
variations.
Furthermore, shrinking device geometry while scaling device parameters and
operating conditions in accordance makes the transistor performance more sensitive
to variations. This trend due to short-channel effects can be noticed for leakage
currents and speed. For instance, the sensitivity of the I
on
current that depends on the
effective channel length L
eff
, the supply voltage, and the effective carrier mobility
μ
eff
that depends on the channel doping N
ch
increases over technology generations
[11] and makes the delay times more sensitive against parameter variations.
In order to reduce the consequences of these developments, new technology
innovations and device architectures as strained silicon, silicon-on-insulator, very
high mobility devices, and for instance trigate transistors have been developed (see
more information, for instance, in [6,9, 12]).

would allow to
determine the probability distribution of Y with the help of Monte Carlo simulation
studies. Using a simplified approach, expected tolerances of the performance
parameter can be estimated. f is replaced by its first-order Taylor series at the
operating point. The parameters shall be Gaussian distributed, where
μ
i
is the mean
or nominal value of the ith parameter and
σ
i
is its standard deviation. Thus for
“small” parameter variations, Y can be approximated by a first-order Taylor series
Y ≈ y
nom
+
n
∑
i=1
a
i
·(X
i
−
μ
i
), (1.4)
where y
nom
is the nominal value of the investigated performance parameter and a

n
∑
i=1
n
∑
j=i+1
ρ
i, j
a
i
a
j
σ
i
σ
j
, (1.5)
where
ρ
i, j
is the correlation coefficient of the ith and jth parameter.
Let us now built up the sum of n parameters with the same Gaussian distribution
N(
μ
,
σ
) and defining in this way a special performance variable Y
∗
:
Y

σ
2
= n·
σ
. (1.7)
If all delay times of the individual gates are strongly uncorrelated (all correlation
coefficients
ρ
i, j
equal 0), it follows from (1.5)
σ
Y
∗
,uncorrelated
=
√
n ·
σ
. (1.8)
1 Introduction 7
Fig. 1.2
σ
n
of a sum of n variables divided by the standard deviation
σ
of one variable
σ
n
(r)
σ

variations. The behavior is checked for “corner cases.” “Worst case,” “typical case,”
and “best case” are investigated for associated parameter sets of the transistor
models [13].
However, Fig. 1.2 shows that, for instance, the delay time may be overestimated
in this way. The procedure brings to much pessimism into the design flow. The
more intra-die variations have to be taken into account, the more improvements on
analysis methods are necessary.
8 J. Haase and M. Dietrich
1.3.2 Consequences for Methods to Analyze Designs
Design methods for nanoscale CMOS have to consider the variability and uncer-
tainty of parameters predicting the behavior of a circuit. There is an impact of
challenges in nanoscale technology on EDA tool development [14]. A number of
methods are available to take variability into consideration.
The compact device models represent a link between the characteristics of the
manufacturing process and the methods that shall predict the behavior of a semi-
conductor circuit. Interactions that are understood can be expressed in a systematic
way by deterministic mathematical models. Phenomena that are poorly understood
are often described by stochastic models. Thus, the choice of an appropriate model is
essential for the subsequent conclusions. The Berkeley Short-channel IGFET Mod-
els are state-of-the-art compact MOS models. BSIM3 was a first industry-wide used
model. It was extended to the BSIM4 model in order to describe MOSFET physical
effects in the sub-100nm regime. These models are based on threshold voltage
formulations. The new PSP model is a surface-potential based model. It promises
an accurate description of the moderate inversion region that becomes a larger part
of the voltage swing as the supply voltage is scaled down [15]. The behavior in the
time domain as well as the leakage behavior must be covered by the models in use.
Several methods have been developed and implemented to extract parameters of
compact models either from measurement or based on device simulations [16]. For
statistical design methods, the knowledge of the probability characteristics of the
parameters is necessary. Various methods have been developed to determine these