VFP Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
C4-93
Notes
Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FSQRTS
performs just one square root operation, and vec_len=1, Sd[0]=Sd, and Sm[0]=Sm.
When the LEN field indicates a vector mode (vector length > 1), FSQRTS might perform
more than one square root operation. Addressing Mode 3 - Single-precision vectors
(monadic) on page C5-14 describes how FSQRTS encodes the registers it uses and how
vec_len, Sd[i], and Sm[i] are determined.
Rounding This is a fully-rounded square root operation. The FPSCR determines the rounding mode.
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VFP Instructions
C4-94
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1.51 FSTD
The FSTD (Floating-point Store, Double-precision) instruction stores a double-precision register to
memory.
Syntax
FSTD{<cond>} <Dd>, [<Rn>{, #+/-(<offset>*4)}]
where:
<cond> Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.
<Dd> Specifies the source register.
<Rn> Specifies the register holding the base address for the transfer.
<offset> Specifies an offset to be multiplied by 4, then added to the base address (if U == 1) or
subtracted from it (if U == 0) to form the actual address of the transfer. If offset is
omitted, it defaults to +0.
Architecture version

Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1.52 FSTMD
The FSTMD (Floating-point Store Multiple, Double-precision) instruction stores a sequence of consecutive
double-precision registers to memory.
Syntax
FSTM<addressing_mode>D{<cond>} <Rn>{!}, <registers>
where:
<cond> Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Specifies the addressing mode, which determines the values of start_address and
end_address used by the instruction. See Addressing Mode 5 - VFP load/store multiple
on page C5-24 for details.
<Rn> Specifies the base register used by <addressing_mode>.
! Sets the W bit of the instruction to 1, specifying that the base register <Rn> is to be updated
by the instruction. If it is omitted, the W bit of the instruction is set to 0 and the base register
<Rn> is left unchanged. Some combinations of <addressing_mode> and the presence
or absence of ! are not allowed. For details, see Addressing Mode 5 - VFP load/store
multiple on page C5-24.
<registers>
Specifies which registers are to be stored, as a list of consecutively numbered
double-precision registers, separated by commas and surrounded by brackets. It is encoded
in the instruction by setting Dd to the number of the first register in the list, and offset to
twice the number of registers in the list. At least one register must be specified in the list.
For example, if <registers> is {D2,D3,D4}, the Dd field of the instruction is 2 and
the offset field is 6.
Architecture version
D variants only
Exceptions

UNPREDICTABLE
.
This happens in two cases:
•if offset == 0, that is, if an attempt is made to transfer no registers
•if d + offset/2 > 16, that is, if an attempt is made to transfer another register
after D15.
Conversions If an implementation uses an internal format for double-precision values, it must convert
that format back to the external double-precision format. Otherwise, no conversion is
required.
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VFP Instructions
C4-98
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1.53 FSTMS
The FSTMS (Floating-point Store Multiple, Single-precision) instruction stores a sequence of consecutive
single-precision registers to memory.
Syntax
FSTM<addressing_mode>S{<cond>} <Rn>{!}, <registers>
where:
<cond> Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Specifies the addressing mode, which determines the values of start_address and
end_address used by the instruction. See Addressing Mode 5 - VFP load/store multiple
on page C5-24.
<Rn> Specifies the base register used by <addressing_mode>.
! Sets the W bit of the instruction to 1, specifying that the base register <Rn> is to be updated
by the instruction. If it is omitted, the W bit of the instruction is set to 0 and the base register
<Rn> is left unchanged. Some combinations of <addressing_mode> and the presence

Notes
Encoding If P=1 and W=0, the instruction is instead an FSTS instruction.
Vectors The FSTMS instruction is unaffected by the LEN and STRIDE fields of the FPSCR, and
does not wrap around at bank boundaries in the way that vector operands to data-processing
instructions do. Registers are stored in simple increasing order of register number.
Invalid register lists
If Fd, Dd and offset do not specify a valid register list, the instruction is
UNPREDICTABLE
.
This happens in two cases:
•if offset == 0, that is, if an attempt is made to transfer no registers
•if d + offset > 32, that is, if an attempt is made to transfer another register after
S31.
Conversions In the programmer’s model is that FSTMS does not perform any conversion on the value
transferred. The source registers can each contain either a single-precision floating-point
number or an integer. The latter is typically obtained as the result of one of the
floating-point-to-integer conversion instructions.
Implementations are free to hold the values in the source registers in an internal format,
provided that FSTMS converts it to external format and this conversion recovers the correct
data, regardless of whether the register contains a single-precision floating-point number or
an integer.
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VFP Instructions
C4-100
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1.54 FSTMX
The FSTMX (Floating-point Store Multiple, Unknown precision) instruction stores a sequence of
consecutive double-precision registers to memory, in an
IMPLEMENTATION

Data Abort
31 28272625242322212019 1615 1211109876543 0
cond 110PU0W0 Rn Dd 1011 offset
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VFP Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
C4-101
Operation
if ConditionPassed(cond) then
/* d is the number of register Dd; */
/* D(n) is the double-precision register numbered n */
Store registers D(d) to D(d+(offset-3)/2) to memory words
Memory[start_address,4] through to Memory[end_address-4,4]
Usage
FSTMX is used to save VFP register values to memory in circumstances where it is unknown what type of
data they contain. Typical cases of this are:
• in procedure entry sequences when a callee-save procedure calling standard is being used
• in process swap code.
Notes
Encoding If P=1 and W=0, the instruction is instead an FSTD instruction. Otherwise, if offset is
even, the instruction is instead an FSTMD instruction.
Vectors The FSTMX instruction is unaffected by the LEN and STRIDE fields of the FPSCR, and
does not wrap around at bank boundaries in the way that vector operands to data-processing
instructions do. Registers are stored in simple increasing order of register number.
Invalid register lists
If Dd and offset do not specify a valid register list, the instruction is
UNPREDICTABLE
.
This happens in two cases:

<Sd> Specifies the source register. Its number is encoded as Fd (top 4 bits) and D (bottom bit).
<Rn> Specifies the register holding the base address for the transfer.
<offset> Specifies an offset to be multiplied by 4, then added to the base address (if U == 1) or
subtracted from it (if U == 0) in order to form the actual address of the transfer. If this
offset is omitted, it defaults to +0.
Architecture version
All
Exceptions
Data Abort
Operation
if ConditionPassed(cond) then
if (U == 1)
address = Rn + offset * 4
else
address = Rn - offset * 4
Memory[address,4] = Sd
31 28272625242322212019 1615 1211109876543 0
cond 1101UD00 Rn Fd 1010 offset
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VFP Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
C4-103
Notes
Addressing mode
This is a special case of Addressing Mode 5 - VFP load/store multiple on page C5-24.
Conversions In the programmer’s model, FSTS does not perform any conversion on the value
transferred. The source register Sd can contain either a single-precision floating-point
number or an integer. The latter is typically obtained as the result of one of the
floating-point-to-integer conversion instructions.

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