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EE 4504 Section 2 1
EE 4504
Computer Organization
Section 2
The Computer System and its
Interconnection Structures
EE 4504 Section 2 2
System Components
At the global and processor levels of
computer design, we are concerned about
four component “primitives”
– CPUs
» ALUs
» Control units
– Memories
– I/O devices
– Interconnection structures
Knowledge of these components and their
operation (interaction) offers insight into
system bottlenecks, alternate pathways,
magnitude of system failures, and
opportunities for performance
enhancement
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EE 4504 Section 2 3
von Neumann’s Architecture
von Neumann is credited with developing
the idea of controlling the operation of
hardware through the manipulation of
control signals

Instruction execution follows a set cycle
– Determine the address of the next instruction
– Fetch that instruction from memory
– Decode the instruction to determine what is to
be performed
– Calculate the addresses of needed operands and
fetch the operands
– Perform the operation on the operands
– Store the results
– Check for and service pending interrupts
Figure 3.12 State diagram for the instruction cycle
EE 4504 Section 2 6
Interrupts
The mechanism by which other system
modules may interrupt the normal
processing of the CPU
These devices are 1-10 orders of
magnitude slower than the CPU
– CPU can waste vast amounts of processing
cycles waiting for these slow devices to
perform their tasks
Interrupts let the CPU execute its normal
instruction sequence and pause to service
the external devices only when they signal
(the interrupts) that they are ready for the
CPU’s attention
The processor and the O/S are responsible
for recognizing an interrupt, suspending
the user program, servicing the interrupt,
and then resuming the user program

» Remaining interrupt requests will be
serviced in turn
– What if an interrupt occurs while an ISR is
being executed (a result of a previous interrupt)
» Ignore the second interrupt (by disabling
interrupts) until the ISR completes -- e.g.,
MC68HC11 microcontroller
» Recognize and service the interrupt only if
it has a higher priority than the one
currently being serviced -- e.g., 8085
EE 4504 Section 2 10
Figure 3.13 Transfer of control with multiple interrupts