6
THE OPERATING SYSTEM
MACHINE LEVEL
1
Level 1
Level 2
Level 3
Operating system machine level
Microarchitecture level
Operating system
Instruction set architecture level
Microprogram or hardware
Figure 6-1. Positioning of the operating system machine level.
Mapping
Address space
Address
8191
4096
0
4095
0
4K Main
memory
Figure 6-2. A mapping in which virtual addresses 4096 to
8191 are mapped onto main memory addresses 0 to 4095.
(a) (b)
Page Virtual addresses
15
14
13
12

5
4
3
2
1
0
Page
frame
Bottom 32K of
main memory
Physical addresses
28672 – 32767
24576 – 28671
20480 – 24575
16384 – 20479
12288 – 16383
8192 – 12287
4096 – 8191
0 – 4095
Figure 6-3. (a) The first 64K of virtual address space divided
into 16 pages, with each page being 4K. (b) A 32K main
memory divided up into eight page frames of 4K each.
Present/absent
bit
Virtual
page
Page
table
15-bit
1

0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
4
0
0
5
0
0
3
0
7
6
0
2
0

10
9
8
7
6
5
4
3
2
1
0
Figure 6-5. A possible mapping of the first 16 virtual pages
onto a main memory with eight page frames.
(a)
Virtual page 7
Virtual page 6
Virtual page 5
Virtual page 4
Virtual page 3
Virtual page 2
Virtual page 1
Virtual page 0
(b)
Virtual page 7
Virtual page 6
Virtual page 5
Virtual page 4
Virtual page 3
Virtual page 2
Virtual page 1

0
Symbol
table
Constant
table
Call
stack
Parse
tree
20K
16K
12K
8K
4K
0
Segment
1
Source
text
Segment
2
Segment
3
Segment
4
Figure 6-8. A segmented memory allows each table to grow or
shrink independently of the other tables.

Consideration Paging Segmentation




























Figure 6-9. Comparison of paging and segmentation.
,,



(5K)
Segment 0
(4K)
(b)
Segment 7
(5K)
Segment 0
(4K)
(c) (d) (e)
Segment 2
(5K)
Segment 7
(5K)
Segment 0
(4K)
Segment 2
(5K)
Segment 5
(4K)
Segment 7
(5K)
Segment 0
(4K)
Segment 2
(5K)
Segment 6
(4K)
Segment 5
(4K)
Segment 7

Word
Page
6-Bit page
number
10-Bit offset
within the page
Two-part MULTICS address
Figure 6-11. Conversion of a two-part
MULTICS
address into
a main memory address.
Bits 13 1 2
INDEX
0 = GDT
1 = LDT
Privilege level (0-3)
Figure 6-12. A Pentium II selector.
Relative
address
0
4
BASE 0-15 LIMIT
BASE 24-31 G D 0 LIMIT 16-19 P DPL TYPE BASE 16-23
0 : LIMIT is in bytes
1 : LIMIT is in pages
0 : 16-bit segment
1 : 32-bit segment
Segment type and protection
Privilege level (0-3)
0 : Segment is absent from memory

Level
Possible uses of
the levels
S
y
s
t
e
m
c
a
l
l
s
S
h
a
r
e
d
l
i
b
r
a
r
i
e
s
U

Virtual
address
51 13
8K Virtual
page number
Offset
Bits
Physical
address
28
8K Page
frame
13
Offset
42 22
4M Virtual
page number
Offset
22
Offset
19
4M Page
frame
Figure 6-17. Virtual to physical mappings on the UltraSPARC.