Appendix C − MAX+plus II Tutorial 2 Page 1 of 11
Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
Contents
Contents ........................................................................................................................................................................ 1

Appendix C

MAX+plus II Tutorial 2.................................................................................................................... 2

C.1

Getting Started .............................................................................................................................................. 2

C.1.1

Preparing a Folder for the Project ......................................................................................................... 2

C.1.2

Creating a Project.................................................................................................................................. 2

C.1.3

Editing the VHDL Source Code............................................................................................................ 2

C.2

Synthesis for Programming the PLD.............................................................................................................3

C.3


C.6.3

Selecting the File to Program.............................................................................................................. 10

C.6.4

Programming the PLD ........................................................................................................................ 11

C.7

Testing the Hardware.................................................................................................................................. 11Appendix C − MAX+plus II Tutorial 2 Page 2 of 11
Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM
Appendix C MAX+plus II Tutorial 2
In tutorial 1, we saw how a VHDL description of a 4-bit counter circuit is synthesized and simulated in
MAX+plus II. Test values for the input signals Clock and Reset were manually setup in the simulator. In order for
the synthesized circuit to operate in hardware, these input signals must be provided for by the hardware. For
example, the Reset signal must be connected to an input switch, and a clock generator is needed for the Clock signal.
Furthermore, the counter output signal Q must be connected to LEDs in order for us to see that the counter is really
working.
In this tutorial, we will expand on the counter circuit by adding a clock generator, and a 7-segment decoder. The
UP2 development board already has a built in clock source running at a frequency of approximately 25MHz. The
clock generator circuit simply divides this clock speed down to 1Hz. The 7-segment decoder converts the 4-bit
counter output to drive a 7-segment LED display. An enclosing entity, top, is used to connect these three entities
(clockdiv, counter, and decoder) together to form one complete circuit. This circuit is then downloaded to the PLD
on the UP2 development board, and after applying power, you can actually see the count being displayed on the 7-
segment LED.
C.1 Getting Started

Figure C-1. Compiler window for full synthesis.
3. From the Compiler window menu, select Processing | Smart Recompile. With this option turned on, if you
change any pin assignments and re-compile, the compiler does not have to perform a full synthesis.
4. Click on the Start button to start the synthesis. You will then see the progress of the synthesis.
5. At the end of the synthesis, if there are no syntax errors, you will see a message window saying that the
compilation was successful. Click OK to close the message window.
C.3 Circuit Simulation
The following steps for circuit simulation in this section are only necessary if you want to perform a simulation
of the circuit. In practice, it is advisable to simulate the circuit to make sure that it is correct before
implementing it on a PLD. For this tutorial, you can skip this step, and go directly to Section 0 for programming
the PLD.
1. From the Manager window menu, select MAX+plus II | Waveform Editor.
2. From the Waveform Editor window menu, select Node | Enter Nodes from SNF. You can also right click under
the Name section in the Waveform Editor window, and select Enter Nodes from SNF from the pop-up menu.
You will see something similar to the Enter Nodes from SNF window shown in Figure C-2.
Appendix C − MAX+plus II Tutorial 2 Page 4 of 11
Microprocessor Design: Principles and Practices with VHDL Last updated 11/19/2003 9:10 AM

Figure C-2. Window for adding signals for simulation.
3. Click on the List button, and a list of available nodes and groups will be displayed in the Available Nodes &
Groups box.
4. Select the signals that you want to see in the simulation trace, and then click on the => button. The signals that
we want are: ResetN, ClockSource, a, b, c, d, e, f, and g. The signals a to g are the signals for driving the
seven LEDs on the 7-segment LED. After clicking on the => button, the selected signals will be moved to the
Selected Nodes & Groups box.
For this particular circuit, you may have a slight problem with the simulation, because the signal ClockSource is
assumed to be running at 25MHz, and the Clockdiv circuit divides the clock down from 25MHz to 1Hz. So to
even see a few counts, you will need the simulation end time to be very large. Two possible solutions to make
the simulation work are to remove the Clockdiv entity from the circuit, or modify the clock divide VHDL code
so that it does not divide the clock.

C.4.1 Selecting the Target Device
1. Open the Device selection window by selecting Assign | Device from the Manager window menu as shown in
Figure C-5.