Systems Design & Programming Memory I CMPE 310
1 (Feb. 25, 2002)
UMBC
U M B C
U
N
I
V
E
R
S
I
T
YO
FM
A
R
Y
L
A
N
DB

• Static RAM (SRAM)
• Dynamic RAM (DRAM)
Generic pin configuration:
A
0
A
1
A
N
O
0
O
1
O
N
Address connection
Output/Input-output connection
...
...
WE
Write
OE
CS
Read
Select
Systems Design & Programming Memory I CMPE 310
2 (Feb. 25, 2002)
UMBC
U M B C
U

M
O
R
EC
O
U
N
T
Y
1

9

6

6
Memory Chips
The number of address pins is related to the number of memory locations.
Common sizes today are 1K to 256M locations.
Therefore, between 10 and 28 address pins are present.
The data pins are typically bi-directional in read-write memories.
The number of data pins is related to the size of the memory location.
For example, an 8-bit wide (byte-wide) memory device has 8 data pins.
Catalog listing of 1K X 8 indicate a byte addressable 8K memory.
Each memory device has at least one chip select (
CS) or chip enable (CE) or
select (

N
DB
A
L
T
I
M
O
R
EC
O
U
N
T
Y
1

9

6

6
Memory Chips
Each memory device has at least one control pin.

T
YO
FM
A
R
Y
L
A
N
DB
A
L
T
I
M
O
R
EC

R
S
I
T
YO
FM
A
R
Y
L
A
N
DB
A
L
T
I
M
O
R
E

9
20
19
18
17
16
15
14
13
10
2716
11
12
21
22
23
24
A
6
A
5
A
4
A
3
A
2
A
1
A

A
0
-A
10
PD/PGM
CS
O
0
-O
7
Address
Power down/Program
Chip Select
Outputs
Chip Select
PWR Down
Prog Logic
Y
Decoder
X
Decoder
CS
PD/PGM
Address Inputs
Data Outputs
Output
Buffers
Y-Gating
16,384
Cell Matrix