4
Data Conversion in Software
Defined Radios
Brad Brannon, Chris Cloninger, Dimitrios Efstathiou,
Paul Hendriks, Zoran Zvonar
Analog Devices
Data converters are one of the key enabling technologies for the software defined radio
(SDR). Regardless of the interpretation of the definitions – software radio, software defined
radio, software based radios – the challenge of moving the analog-digital boundary closer to
the antenna is the critical step in establishing the foundation for increasing the content and
capability of digital signal processing (DSP) in the radio. SDR technologies have provided
the incentives for the breakthrough in converter technologies pushing the state-of-the-art [1].
In this chapter we review the foundations and technologies of data conversion from the
perspective of their usage in SDRs, exploring capabilities, constraints, and future potential.
4.1 The Importance of Data Converters in Software Defined Radios
The use of converters in SDR depends upon the overall radio architecture. A summary of
sampling techniques for the various receiver architectures described in Chapters 2 and 3 is
given in Table 4.1.
Table 4.1 Summary of sampling strategies for SDR receivers
Radio RX architecture Analog output Sampling strategy
Direct conversion I/Q baseband Quadrature baseband
Superheterodyne I/Q baseband Quadrature baseband
IF signal IF sampling
Bandpass sigma-delta
Low IF IF frequency – quarter of
sampling frequency
Direct sampling
Software Defined Radio
Edited by Walter Tuttlebee
Copyright q 2002 John Wiley & Sons, Ltd
ISBNs: 0-470-84318-7 (Hardback); 0-470-84600-3 (Electronic)

Multimode solution supports several radio standards, and SDR is the cost- effective way to
establish multimode solution. This approach minimizes multiple radio functions (for
different standards) in favor of a multimode high performance radio per antenna. The
signal for each standard is processed in the digital domain. This type of solution provides
the often necessary upgrade capability from legacy systems to new standards.
†
Reconfigurable base stations provide software and possibly hardware (programmable
filters, field programmable gate arrays (FPGAs), systolic arrays) reconfiguration based
on the air interface.
In all cases, ADC is critical for the system operation. Base station architectures may take
into consideration either quadrature baseband sampling or IF sampling. For a given frequency
band (dependant on the air interface) the analog front end can be optimized; it is, however,
kept fixed, which is more cost effective today than having a frequency agile and bandwidth
programmable front end SDR implementation. The system clock is fixed, providing uniform
sampling of the analog signal.
The analog front end has a direct impact on the ADC dynamic range [4]. Wideband IF
Software Defined Radio: Enabling Technologies100
sampling front end linearity is critical for intermodulation generation, and selectivity is
significant for blocking attenuation. Requirements of the given wireless air interface signifi-
cantly impact ADC specification in terms of dynamic range and spurious free dynamic range
(SFDR). Factors influencing the dynamic range of the converter in wireless systems include
statistical properties of the input signal, peak to average ratio, level of the interference,
frequency of the interfering signal compared to aperture jitter, fading margin, etc. [5]. Selec-
tion of the bandwidth to be digitized depends on the maximum sampling rate and dynamic
range of an ADC. Approximately one bit of the resolution is lost for every doubling of the
sampling rate [1].
Base station designs rely on best available converters in the class with highest resolution
and widest operating bandwidth. Available state-of-the-art ADCs for wireless applications
are 14-bit resolution devices operating in excess of 100 MHz, but there is an increased
demand from base station manufacturers for 16-bit ADCs operating in excess of 120 MHz.

Data Conversion in Software Defined Radios 101
usually given less attention, although the problem is of comparable complexity [6]. High
performance digital-to-analog converters (DACs) are specifically used in the transmit (Tx)
signal path to reconstruct one or more carriers that have been digitally modulated. More of the
signal processing in these new generations of communication equipment is being performed
in the digital domain for multiple reasons (i.e. higher spectral efficiency thus higher capacity,
improved quality, added services, software programmable, lower power, etc.). Furthermore,
many of these DSP functions are being integrated with the DAC itself to enhance its perfor-
mance and to enable new transmitter architectures. These DSP functions may range from
digital interpolation filters, which reduce the complexity and cost of the required analog
reconstruction filter, to complete application specific digital modulators for quadrature or
spread spectrum modulation schemes.
Synthesizing communication signals in the digital domain typically allows the character-
istics of a signal to be precisely controlled. However, in the reconstruction process of a
digitally synthesized signal, it is the DAC and its nonideal characteristics which often
yield unpredictable results. In some cases, it is the performance of the DAC which actually
determines whether a particular modulation scheme or system architecture can meet the
specification. Unlike high speed video DACs, the performance of DACs in wireless systems
is often analyzed in the frequency domain, with secondary consideration given to the time
domain and DC specifications. Selecting the optimum DAC for a given wireless system
requires an understanding of how to interpret various specifications and an appreciation of
their effects on system performance. Achieving the optimum performance while realizing
other system objectives demands careful attention to various analog interface issues.
Much design effort has gone into improving the frequency domain and static performance
of these devices while meeting other system objectives such as single supply operation, lower
power consumption, lower costs, and ease of digital integration. To that extent, several
semiconductor vendors realizing the significance of the above stated objectives as well as
industry trends have elected to focus much of their effort on designing high -performance
DACs on a digital CMOS process. State-of the-art DACs are 14-bit devices with SNR higher
than 80 dBc and sampling rate of 400 Msamples/s. Third-order intermodulation distortion is

the chip, costs, and complexity increase at an exponential rate of 2
N
. Although not impossible
to design and build, in practice there are very few flash ADCs larger than 10 bits because of
the relatively large die sizes. Beyond this point they are too big and complex to manufacture
efficiently, thus adversely impacting on cost. To overcome the complexity problem, different
Data Conversion in Software Defined Radios 103
Figure 4.1 Typical flash ADC architecture
architectures have been developed which use fewer comparators such as in folded flash or
pipelined architectures.
In addition, as the number of comparators increases, the reference voltages get smaller and
smaller. As the reference voltage is reduced, the offset voltage of the comparator is
approached. Once this happens, the linearity and overall performance of the converter is
compromised.
Finally, as more comparators are connected to the analog input, the input capacitance
increases. With the increased capacitance, the effective signal bandwidth is reduced, defeat-
ing the high speed benefit of the parallel converter.
In addition to these impediments, there are several anomalies associated with the flash
architecture. The first is basic linearity. The overall linearity of a flash converter is determined
by the linearity of the resistive ladder. If not properly constructed, the differential nonlinearity
(DNL) and integral nonlinearity (INL) requirements of the converter will not be met. Addi-
tionally, because comparators have input leakage currents, these additional currents in the
ladder can affect both the DNL and INL of even a perfectly constructed ladder. As discussed
later, both of these converter parameters can adversely affect the performance of a receiver
(Figure 4.1).
4.2.2 Multistage Converters
Another popular architecture used in high speed, high resolution ADC is the multistage
architecture. One of the key advantages of this architecture is its scalability. The end resolu-
tion can be manipulated easily by increasing and decreasing the bit precision of each stage.
Obviously there are trade-offs in doing this, but conceptually it is possible to extend this

lower overall cost.
Although a multistage ADC has many advantages, it does have some very challenging
design requirements. As mentioned above, this architecture places strict requirements on the
first conversion stage DAC (DAC1). Because this DAC (DAC1) represents the reference for
the entire ADC, it must have a resolution greater than the overall number of bits for the entire
ADC. With today’s technology, it is possible to achieve up to 16 bits of resolution for this
type of DAC.
4.2.3 Sigma-Delta Converters
The sigma-delta (also known as delta-sigma) ADC is a highly innovative and relatively new
idea in ADC technology. In wireless applications the SD ADC can offer integration with
other RF/IF functions to build highly optimized integrated circuit (IC) devices.
As shown in Figure 4.3, the SD ADC consists of an analog filter, a quantizer (comparator),
a decimation digital filter circuit, and a DAC. An n-bit comparator tells the output voltage in
Data Conversion in Software Defined Radios 105
Figure 4.3 Sigma-delta ADC
which direction to go, based upon what the input signal is doing. It looks at the input and
compares it with its last sample to see if this new sample is bigger or smaller than the previous
one. If it is bigger, then it tells the output to keep increasing; if it is smaller, it tells the output
to stop increasing and start decreasing. SD modulators work by sampling faster than the
Nyquist criterion and making the power spectral density of the noise nearly zero in a narrow
band of signal frequencies (quantization noise shaping). Oversampling pushes out the noise,
but it does so uniformly – that is, the spectrum is still flat [7]; noise shaping changes that.
Noise shaping contours the quantization noise. Conservation still holds, the total noise is the
same, but the amount of noise present in the signal band of interest is decreased while
simultaneously increasing the out-of-band noise. A series of decimation filters is used to
remove any undesirable components (undesirable interferers and/or noise not sufficiently
filtered in the analog domain) while simultaneously reducing the data rate in accordance
with the target signal’s bandwidth. Depending on the modulation scheme, the complex data
rate (hence decimation factor) is set to be at least a factor of two greater than the channel
bandwidth, to allow for further postprocessing. There is no one-to-one correspondence

ADC can be increased to n 1 1 bits by oversampling the signal by a nominal factor of 4 and
Software Defined Radio: Enabling Technologies106
subsequently digitally lowpass filtering to the Nyquist rate [8]. The lowpass filtering can
require a number of stages of comb filters and multibit finite impulse response (FIR) filters,
and is actually an expensive requirement (in digital circuitry terms). The trade-off when using
sigma-delta ADC devices is an increase in the digital processing requirements against a
reduction in the provision of accurately trimmed analog components and complexity.
Sigma-delta ADCs are well suited for use in SDR, either for direct sampling or for
bandpass sampling. By employing a bandpass loop filter and feedback around a coarse
quantizer, bandpass modulators shape quantization noise away from narrowband signals
centered at intermediate frequencies. This approach, first successfully integrated in [9],
eliminates the need for dual in-phase/quadrature-phase analog mixers and the separate low
pass ADC converters generally used for each quadrature channel. Instead, demodulation is
now moved into the digital domain, thereby eliminating the problem of channel mismatch
[10]. Furthermore, since the conversion is performed directly on the IF signal before mixing
to baseband, the modulator does not suffer the effects of DC offset and low frequency noise
problems.
4.2.4 Digital-to-Analog Converters
Most high speed CMOS DACs (including bipolar and BiCMOS) employ an architecture
based on current segmentation and edge-triggered input data latches to achieve the desirable
code independent settling and glitch impulse characteristics that are necessary to maintain
low distortion. Figure 4.4 shows a typical segmentation architecture common among many
CMOS DACs. Typically, the upper 4 or 5 binary-weighted bits (MSBs) are implemented as
thermometer decoded, identical current sources and switches. To optimize DC linearity
performance, each of these identical current sources may consist of an array of unit current
sources. The middle binary-weighted bits (LSBs) are implemented using a similar current
Data Conversion in Software Defined Radios 107
Figure 4.4 Example of a segmented current source architecture used for a 14-bit CMOS DAC
segmentation based on these unit current sources. The remaining LSBs consist of binary
weighted current sources.

current outputs can easily be converted to two single ended or one differential voltage output
by using resistive loads, a transformer, or an op amp.
Beyond this common architectural approach lie various differences in the actual imple-
mentation, affecting a high speed DAC performance and system requirements. For exam-
ple, to improve upon their DC linearity performance, many 12- and 14-bit CMOS DACs
use some form of factory calibration technique. A typical calibration procedure attempts
to trim the current sources of the MSB segmentation to equal each other, and the sum of
Software Defined Radio: Enabling Technologies108
Figure 4.5 Differential switches steer current into one of two output nodes allowing for differential or
single-ended operation