Download miễn phí Khóa luận A soft error tolerant sram design in 130nm cmos technology



TABLE OF CONTENTS
Acknowledgement
Abstract
Table of contents
Abbreviations
List of tables
List of figures
CHAPTER 1 - INTRODUCTION . 1
1.1. Problem and motivation . 1
1.2. Contribution of the thesis . 2
1.3. Thesis organization . 2
CHAPTER 2 - BACKGROUND . 4
2.1. Soft errors in semiconductor device . 4
2.1.1. Radiation sources . 4
2.2. Soft errors occurrence mechanism . 5
2.3. Soft errors mitigation techniques . 6
2.3.1. Device level techniques . 6
2.3.2. Circuit level techniques . 7
2.3.3. Block level techniques . 7
CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN . 10
3.1. SRAM specification . 10
3.1.1. General information . 10
3.1.2. Floorplan . 11
3.1.4. Operation brief description . 12
3.2. SRAM detail design . 14
3.2.1. SRAM cell architecture . 14
3.2.2. Replica path for Read operation . 15
3.2.3. Internal clock generator . 17
3.2.4. Write circuit . 19
3.2.5. Decoder . 19
3.2.6. Input/output latches . 21
3.3. Error detecting and correcting (EDC) block . 22
3.3.1. Hamming code algorithm . 23
3.3.2. EDC block implementation . 24
3.3.3. EDC detail architecture . 26
CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION . 37
4.1. SRAM cell simulation . 37
4.1.1. SRAM cell simulation to find device size . 37
4.1.2. SRAM cell characteristic summary . 42
4.1.3. Static noise margin comparison . 43
4.1.4. SRAM cell capacitance . 43
4.2. Soft error tolerant simulation . 44
4.2.1. Verification methodology . 44
4.2.2. Critical charge simulation . 45
4.2.3. Simulation results . 46
4.2.4. Conclusion . 49
4.3. Post-layout simulation . 50
4.3.1. Simulation setup . 50
4.3.2. Cycle time definition and simulation result . 52
4.3.3. Access time . 55
4.3.4. Setup time . 56
4.3.5. Timing delay of some critical paths. 57
4.3.6. Simulation results summary . 61
4.4. SRAM and EDC functional verification . 61
4.4.3. Simulation setup . 65
4.4.4. Functional verification result . 67
4.5. Physical verification . 70
CHAPTER 5 – CONCLUSION AND FUTURE WORK . 75


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· This SRAM was designed in 130nm CMOS technology.
· Operating voltage range is from 1.35V to 1.65V
· Operating frequency is 200MHz (at worst case)
· Hand-crafted layout
· 22 bit data in/out for SRAM
· Only 16 bit data in/out for EDC block interface because the remaining 6 bit
data of SRAM were used as parity bit check.
· 8 row addresses input and 2 column addresses IO
· Two independent clocks for read and write operations as well as two
independent data in/out ports and address buses.
· Some parts of the design were selected to be radiation hardened
· There is also the memory enable control for read and write.
· EDC enable pin allows to operate with or without error detection and
correction task
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3
SOFT ERROR TOLERANT SRAM DESIGN
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3.1.2. Floorplan
MEMORY ARRAY
R
E
F
C
O
L
U
M
N
ROW DECODER
CONTROL BLOCK
R
E
F
I
O
C
E
N
A
REF ROW
BUILT-IN EDC BLOCK
C
E
N
B
A
A
[0
:9
]
A
B
[
0
:9
]
C
E
N
A
C
E
N
B
C
E
N
A
C
E
N
B
A
A
[0
:9
]
A
B
[
0
:9
]
C
E
N
A
C
E
N
B
BUILT-IN EDC BLOCK
Q
A
[0
:2
1
]
D
B
<
0
:2
1
]
B
W
E
N
L
A
T
C
H
Q
I[
0
:2
1
]
Q
I[
0
:2
1
]
R
A
M
_
M
O
D
E
L
A
T
C
H
S
E
D
E
P
E
R
A
M
_
M
O
D
E
D
I<
0
:1
5
]
Q
O
[0
:1
5
]
A
B
[
0
:9
]
A
A
[0
:9
]
C
E
N
B
C
E
N
A
C
E
N
B
C
E
N
A
COLUMN MUX
SENSE AMPLIFIER - OUTPUT BUFFER
Figure 3.1: SRAM floorplan
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 12
3.1.3. Interface pin description
Table 3.1: Pin description
Pin Name Description
CLKA Read port clock input
CLKB Write port clock input
CENB Write enable
CENA Read enable
AA Read address
AB Write address
DI Data in
QO Data output
RAM_MODE EDC block disable pin
· RAM_MODE = 0: the SRAM will work with error detecting
and correcting tasks
· RAM_MODE = 1: the SRAM will work in normal mode,
without error detecting and correcting tasks.
DE Double bit error flag
SE Single bit error flag
PE Parity bit error flag
3.1.4. Operation brief description
3.1.4.1. SRAM operation
A write operation is started at the rising edge of CLKB signal. The write
enable control input, data input and address input are latched at the
beginning of each cycle. During a write operation, data will be written
into the memory, and the data will not propagate to the memory output.
CHAPTER
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 13
The memory output will remain at the value determined by the last
memory read.
Figure 3.2: Write operation
Similarly, a read operation is started at the rising edge of CLKA signal. The
read enable control input and address input are latched at the beginning of
each cycle. The data output latch is latched following each read access,
controlled by the track path.
Figure 3.3: Read operation
3.1.4.2. Built-in EDC operation
In each write operation, the 16 bit data input DI of EDC will be
encoded to 6 parity bits following the Hamming code. After that, 16 bit
data input and 6 parity bits will propagate to 22-bit data in ports
DB of the SRAM. That means, in the memory array, only 16 bit is
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 14
data information, the other 6 bits contain the error correcting code, which
used to detect and fix the data information if there are errors.
In each read operation, the 22 bit data output from SRAM QAwill
propagate to the QI of EDC block. EDC will decode 16 bit data
output read from the SRAM to six check bits. These six checked bit will
be compared with the parity bits read from the memory. If single bit error
occurred, EDC would detect and fix. The SE flag will be on and the data
output is correct data. If double bit error occurred, EDC would detect but
not fix. The DE flag will be on to indicate there is a double bit error. The
detail functional of the EDC block will be discussed in EDC architecture
section.
3.2. SRAM detail design
3.2.1. SRAM cell architecture
This SRAM cell was applied the circuit hardening technique [11, 12]. Some
extra transistors were adding to the classic 8 transistors SRAM cell. In detail,
two additional inverters and a control transistor are included as in figure
below. The control transistor is ON when both RWL and WWL are low.
Therefore, this extra protection circuit is only turned on in standby mode.
During the standby mode, the extra transistors will be used to enhance the
charge value of IBL and IBLX, which lead to increase the critical charge value
of these nodes. That means, the soft error tolerant level of this SRAM cell is
improved. The level of soft error tolerant depends a lot on the physical
parameter and characteristic of the extra transistors.
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3
SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 15
Figure 3.4. SRAM cell architecture
Because the protection circuit is OFF during normal mode (read/write), it will
not affect a lot the read and write performance. The level of soft error tolerant
depends a lot on the physical parameter and characteristic of the extra
transistors. Increasing width of extra transistor could enhance the tolerance
level; however, this will trade off with the area overhead.
3.2.2. Replica path for Read operation
WWL WWL
RWL RWL
PENX PENX
WBL
WBL RBL
RBL
WBLX
WBLX
IBLX
IBL
Figure 3.4: SRAM cell architecture
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 16
This design uses the inverter sense; the output latch is enabled by the signal
obtained from the reference column and reference row. Reference column is
an additional column used to generate the enabling signal for the output latch.
It has 256×1 bits and the same bitline capacitance as that in the cell array.
Reference row is an additional row used to generate the reference read
wordline signal which reads the cells in reference column. This additional row
makes the reference read wordline have the same capacitance as that for
wordlines in cell array.
The reference row and column are configured to model the furthest path of the
array. Therefore, ensure that the output latch is opened after the data read from
memory valid. The reference column cell, reference row cell, reference
feedback row cell are the edition of the memcell. In the reference column cell,
the “pull up” pmos transistors are disconnected from the IBL because these
cells are just used to model the bitline capacitance. In the reference row cell,
IBL, IBLX and DMWWL are shorted together while DMWWL is tied to VSS
at XDEC block. The reference feedback row cell is put at the middle of the
array. The DMRWLFB signal is enabled when DMRWL reaches to the
feedback cell. In the reference memcell, IBL and IBLX are tied to high.
DMXDEC
XDEC
CTL
XDEC
REFMEM REFROW REFROWFB REFROW … …
…
REFCOL MCELL MCELL MCELL … …
REFCOL MCELL MCELL MCELL … …
…
IOREF IO IO IO
CPGEN
VC
P
LATCH
DMRWL
DMRWLFB
D
M
RB
L
ECHO
CLKA
Out
latch
Out
latch
Out
latch
QA[0] QA[21] QA[n]
Figure 3.5: Timing scheme for read operation
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 17
During the read operation, both the accessed RWL and the reference RWL go
high. The reference_row_feedback cell enables the DMRWLFB, leads to a
read 0 operation at the reference memcell. The DMRBL is discharged, opens
the output latch, and also sends the echo signal back to reset internal clock.
Figure 3.6 above shows the schematic of reference IO cell and the read circuit
in IO cell. In the cycle low, the DMRBL is pre-charged. When the read
operation is initiated, a read 0 from reference memcell will discharge the
DMRBL. Therefore, send the signal to open the output latch of the read circuit
in the IO cells, the read data then propagate to output port. The output latch is
closed by the falling edge of internal read clock to keep the value of data out.
3.2.3. Internal clock generator
3.2.3.1. Read clock generator circuit
LATCH
Mux
select
RMSE RMSE
RB
L<
0:
3>
RHCPX
Output
latch
Figure 3.6: Reference IO cell and read circuit
CHAPTER
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SOFT ERROR TOLERANT SRAM DESIGN
P a g e | 18
A read operation is starting by the rising edge of CLKA. Signal
PULDOWN is delayed from CLKA to pull the INTCLKX down to VSS.
Rising edge on LCP pulse is sent to IO block to start a read operation. As
mention in the 3.2.2 section, when the DMRBL is discharged, an echo
signal will be sent back to read clock generator circuit, indicate that the
high level duration of read clock is enough for a read operation, then the
LCP signal will be reset (RESETX...

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