ELEC-2005
Electronics in High Energy Physics
Winter Term: Introduction to Electronics in HEP
Field Programmable Gate Arrays
Part 1
Stefan Haas
[email protected]
CERN Technical Training 2005
Stefan Haas, 1 F
eb. 2005
ELEC-2005 2
Part 2
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VHDL
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Introduction
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Examples
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Design Flow
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Entry Methods
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Simulation
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Synthesis
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Place & Route
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IP Cores
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Advantages (compared to an ASIC):
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Low development costs
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Short development cycle
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Device can (usually) be reprogrammed
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Types of programmable logic:
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Complex PLDs (CPLD)
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Field programmable Gate Arrays (FPGA)
CPLD
Architecture and Examples
Stefan Haas, 1 F
eb. 2005
ELEC-2005 6
PLD - Sum of Products
A B C
CBACBAf ••+••=
1
CBABAf ••+•=
2
AND plane
Programmable AND array followed by fixed fan-in OR gates
Programmable switch or fuse
Stefan Haas, 1 F
eb. 2005

Interconnection Matrix
Interconnection Matrix
I/O Block
I/O Block
I/O Block
I/O Block
PLD
Block
PLD
Block
PLD
Block
PLD
Block
I/O Block
I/O Block
I/O Block
I/O Block
•

•

•

Interconnection Matrix
Interconnection Matrix
•

•


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Programmable logic blocks
Implement combinatorial and
sequential logic
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Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
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Programmable I/O blocks
Special logic blocks at the
periphery of device for external
connections
I/O
I/O
Logic block
Interconnection switches
I/O
I/O
Stefan Haas, 1 F
eb. 2005
ELEC-2005 13
Other FPGA Building Blocks
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Clock distribution
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Embedded memory blocks
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Special purpose blocks:
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Clock
Stefan Haas, 1 F
eb. 2005
ELEC-2005 15
Look-Up Tables (LUT)
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Look-up table with N-inputs can be used to implement any
combinatorial function of N inputs
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LUT is programmed with the truth-table
LUT
LUT
A
B
C
D
Z
A
B
C
D
Z
Truth-table Gate implementation
LUT implementation
Stefan Haas, 1 F
eb. 2005
ELEC-2005 16
LUT Implementation
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Example: 3-input LUT

eb. 2005
ELEC-2005 17
Programmable Interconnect
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Interconnect hierarchy (not shown)
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Fast local interconnect
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Horizontal and vertical lines of various lengths
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
Switch
Matrix
Switch
Matrix
Stefan Haas, 1 F
eb. 2005
ELEC-2005 18
Switch Matrix Operation
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DSP blocks
Stefan Haas, 1 F
eb. 2005
ELEC-2005 20
Configuration Storage Elements
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Static Random Access Memory (SRAM)
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each switch is a pass transistor controlled by the state of an SRAM bit
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FPGA needs to be configured at power-on
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Flash Erasable Programmable ROM (Flash)
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each switch is a floating-gate transistor that can be turned off by
injecting charge onto its gate. FPGA itself holds the program
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reprogrammable, even in-circuit
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Fusible Links (“Antifuse”)
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Forms a forms a low resistance path when electrically programmed
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one-time programmable in special programming machine
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radiation tolerant
Example: Altera Stratix Series
Stefan Haas, 1 F
eb. 2005
ELEC-2005 22

ELEC-2005 25
Embedded Memory
Dual-Port RAM
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M512 – 512 x 1
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M4K – 4096 x 1
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M-RAM – 64K x 8