283

Digital Logic Testing and Simulation

,

Second Edition

, by Alexander Miczo
ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc.

CHAPTER 6

Automatic Test Equipment

6.1 INTRODUCTION

Digital circuits have always been designed to operate beyond the point where they
could be reliably manufactured on a consistent basis. It is a simple matter of eco-
nomics: By pushing the state of the art—that is, aggressively shrinking feature sizes,
then testing them and discarding those that are defective—it is possible to obtain
greater numbers of ICs from a single wafer than if they are manufactured with more
conservative feature sizes (cf. Section 1.8 for more discussion on this practice).
This strategy depends on having access to complex, and sometimes very expen-
sive, test equipment. This strategy also depends on being able to amortize tester cost
over many hundreds of thousands, or millions, of ICs. As ICs become more complex,
running at faster clock speeds, with greater numbers of I/O pins, requirements on the
tester become greater. More pins must be driven and monitored. Tolerances grow
increasingly tighter, and there is less margin for error. Clock skew and jitter must be
controlled more tightly, and the increasing amount of logic, running at ever higher

sample the response at output pins after sufficient time has elapsed to permit signals
to propagate and settle out. The tester then compares sampled response to expected
response in order to determine whether the DUT responded correctly to applied
stimuli. Depending on their capabilities, these testers can be used to test for correct
function, characterize and debug initial parts, and perform speed binning.

6.2.1 The Static Tester

Functional testers can be characterized as static or dynamic. A

static tester

, such as
the one depicted in Figure 6.1, applies all signals simultaneously and samples all
output pins at the end of the clock period. Device response is compared to the
expected response and, if they do not match, the controlling computer is given
relevant information such as the vector number and the pin or pins at which the
mismatch was detected. The static tester does not attempt to accurately measure

when

events occur. Therefore, if a signal responds correctly but has excessive propa-
gation delay along one or more signal paths, that fact may not be detected by the
static tester. These testers are primarily used for go–nogo production testing.
A general-purpose tester must have enough pins to drive the inputs and to monitor
the outputs of the DUT. In fact, in order to be general purpose, the tester must have
enough pins to drive and sample the I/Os of the largest DUT that might be tested by
that tester. Furthermore, since it is not known how many of the I/Os on the DUT are
inputs, and how many are outputs, it must be possible to configure each of the tester
pins as an input or as an output. If a device has more pins than the tester, it may be

BASIC TESTER ARCHITECTURES

285

When considering a tester for purchase, its maximum operating speed may be an
important consideration, depending on the purpose for which it is being purchased.
But other factors, including accuracy, resolution, and sensitivity, must be given
equal weight.

1
Accuracy

is a measure of the amount of uncertainty in a measure-
ment. For example, if a voltmeter is rated at an accuracy of ±0.1% and measures
5.0 V, the true voltage may lie anywhere between 4.95 V and 5.05 V.

Resolution

refers to the degree to which a change can be observed. Referring again to the volt-
meter, if it is a digital voltmeter, its resolution is expressed as a number of bits. How-
ever, the last few bits may not be meaningful if measurements are being taken in a
noisy environment. If the noise is random and there is a need for greater resolution,
samples can be averaged. This is done at the expense of sampling rate.

Sensitivity

describes the smallest absolute amount of change that can be detected

the test program that defines input stimuli and expected response is directed to

pin
memory

. Behind each channel on the tester there is a certain amount of pin memory
capable of storing the stimuli and response for that particular channel. The goal is to
have enough memory behind each tester channel to store an entire test sequence.
However, testers may allow pin memory to be reloaded with additional stimuli and
response from the hard drive. When refreshing pin memory, each memory load may
require an initialization sequence, particularly if the DUT contains dynamic parts.
Some parts may also run very hot, and the additional time on the tester, waiting for
pin memory to be updated, may introduce reliability problems for the part.
Many of the pins on a typical DUT may be bidirectional pins, acting sometimes
as inputs and sometimes as outputs. Therefore, on a general-purpose tester, it must

286

AUTOMATIC TEST EQUIPMENT

be possible to dynamically change the function of the pins so that during execution
of a test a tester channel may sometimes drive the pin that it is connected to, and
sometimes sample that same pin. This and other pieces of information must be pro-
vided in the test program developed by the test engineer. Other information that
must be provided includes information such as voltage and current limits. A subse-
quent section will examine a tester language designed to configure tester channels
and control the tester.

6.2.2 The Dynamic Tester


into hardware in order to provide resolution in the picosecond range.
The dynamic tester solves some problems, but in doing so it introduces others.
Whereas the static tester employs low slew rates (the rate at which the tester changes
signal values at the circuit inputs), the dynamic tester must employ high slew rates
to avoid introducing timing errors. However, high slew rates increase the risk of
overshoot, ringing, and crosstalk.

2

Programming the tester also requires more effort
on the part of the test engineer, who must now be concerned not only with the signal
values on the circuit being tested but also with the time at which they occur. The task
is further complicated by the fact that these timings are also dynamic, being able to
change on a vector-by-vector basis, as different functions inside the IC control or
influence the signal directions and logic values on the I/O pins.
The architecture of a dynamic tester is illustrated in Figure 6.2.

3

The test pattern
source is the same set of patterns that are used by the static tester. However, they are
now controlled by timing generators and wave formatters. The test patterns are
initially loaded into pin memory and specify the logic value of the stimulus or the
expected response. The remaining circuits specify when the stimulus is to be applied
or when the response is to be sampled. The system is controlled by a master clock

BASIC TESTER ARCHITECTURES

287



Another factor that makes the tester-
per-pin more accurate is the fact that there is always one fixed-length signal path to
the DUT, so the timing can be calibrated for that one path.

Figure 6.3

Architecture of tester-per-pin tester.
Master
clock
DUT
Timing
generators
N × M Switching
matrix
Wave
formatters
Pin
electronics
Master
clock
DUT
Timing
generators
Wave
formatters
Pin
electronics

288

and so on, for multiple-test programming languages.
The Standard Test Interface Language (STIL) was designed to provide a common
programming language that would let test engineers write a test program once and
port it to any tester. It has been approved by the Institute of Electrical and Electronic
Engineers (IEEE) as IEEE-P1450.

5

Its goal is to be “tester independent.”

6

This is
achieved by having the language represent data in terms of its intent rather than in
terms of a specific tester.

7

Thus, it is left to the tester companies to leverage to full
advantage all of the features of their particular testers, given a test program written
in STIL.
STIL provides support for definition of input stimuli and expected response data
for test programs. But it also provides mechanisms for defining clocks, timing infor-
mation, and design-for-test (DFT) capabilities in support of scan-based testing. One
of its capabilities is a ‘UserKeywords’ statement that supports extensibility by
allowing the user to add keywords to the language. STIL was initiated as a tool for
describing test programs for testers, but its flexibility and potential have made it
attractive as a tool for defining input to simulation and ATPG tools. It also offers an
opportunity to reduce the number of data bases. Rather than have several data bases
to capture and hold data and results from different phases of the design, test, and

0

–

Q

7

. It will have an
asynchronous, active low clear, an active-high output OE, and a clock with active
positive edge. When OE is low, the output of the register floats to Z.

Example

STIL 0.0;
// 8-bit Reg. with clock and clear
Signals {
CLK In;
CLR In;
OE In;
D0 In; D1 In; D2 In; D3 In; D4 In; D5 In; D6; In; D7 In;
Q0 Out; Q1 Out; Q2 Out; Q3 Out; Q4 Out; Q5 Out; Q6 Out;
Q7 Out;
}
SignalGroups {
INBUS ‘D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7’;
OUTBUS ‘Q0 + Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7’;
ALL ‘CLK + CLR + OE + INBUS + OUTBUS’;
}
Spec timingspec {

CLK { 01 { ‘0ns’ ForceDown/ForceUp;
CLK_edge: ‘25ns’ ForceUp/Forcedown; }}
INBUS { 01 { ‘0ns’ ForceDown/ForceUp; }}
OUTBUS { L { ‘0ns’ X; ‘CLK_edge+tpzl’ l;
‘@+strobe_width’ X;}
H { ‘0ns’ X; ‘CLK_edge+tpzh’ h; ‘@+strobe_width’ X;}
D { ‘0ns’ X; ‘CLK_edge+tplz’ t; ‘@+strobe_width’ X;}
U { ‘0ns’ X; ‘CLK_edge+tpzh’ t; ‘@+strobe_width’ X;}
F { ‘0ns’ X; ‘CLK_edge+tphl’ l; ‘@+strobe_width’ X;}
R { ‘0ns’ X; ‘CLK_edge+tplh’ h; ‘@+strobe_width’ X;}
X { ‘0ns’ X; } }
} // end Waveforms
} // end WaveformTable first_group
} // end Timing
PatternBurst stimuli {
PatList { exercise_part; }
}
PatternExec {
Timing timing_info;
Selector typical_mode;
Category prop_time;
PatternBurst stimuli;
} // end PatternExec
Pattern exercise_part {
W first_group;
// first vector must define states on all signals
V { ALL=00000000000XXXXXXXX; } // clear the reg’s,
// don’t measure
V { CLR=1; OUTBUS=XXXXXXXX; } // release the clear,
// don’t measure

defining the WaveformTable. The names of the Spec entries are arbitrary and, in fact,
any number of entries could be used in the Spec block. For example, a user may have
a legitimate reason to define unique propagation times from X to Z, 0, and 1.
Three values, a minimum, typical, and maximum, are assigned to each of the six
variables in the Spec block. A seventh variable called strobe_width has one value
that defines the duration of a strobe measurement on an output. The Selector block
determines which of the Spec values to use. There are four possibilities: Min, Typ,
Max, or Meas. Meas values are determined and assigned during test execution time;
they are not explicitly specified in the Spec information.
The Timing block follows the Selector block. It is given the name timing_info. It
contains definitions for one or more WaveformTables. In the example presented here
there is just one WaveformTable, and it is assigned the name first_group. The first
statement assigns a period of 50 ns to all the test vectors that use first_group. Then,
some Waveforms are defined. The first one is for CLR, the clear signal. The number
0 follows the signal name CLR. It is called a WaveformChar, abbreviated WFC.
Although any character may be used to represent the waveform following the WFC,
it is good practice to use a character that has some recognizable meaning because
the WFC will be used in the ensuing vectors.
A signal may have several waveforms, but each one must have a different WFC.
In STIL a waveform is a series of time/event pairs. In the waveform for CLR the
keyword ForceDown follows the time 0 ns. So, at time 0 a ForceDown event occurs;
CLR is driven low if it had previously been at a high value. If a signal is in the off
(Z) state, it is turned on and driven low. Notice that in the example given above,

292

AUTOMATIC TEST EQUIPMENT

there are two waveforms for CLR that have identical timing, so they could actually
be merged. However, they were kept separate for illustrative purposes.

which was defined to be CLK_edge + tpzl in the previous field. So @+strobe_width
is 31.00 ns + 3.00 ns, meaning that the tester should continue to monitor OUTBUS
until 34.00 ns.
Each of the first six entries for OUTBUS corresponds to one of the six entries in the
Spec block. The seventh entry is for those vectors where the output is unknown, and
the tester is instructed not to strobe. The letters

l

,

h

, and

t

are called events and indicate
a window strobe. The letter

t

is used when the response is supposed to be high imped-
ance during the entire strobe window. Several other events are defined in P1450.
The PatternBurst block, with the name “stimuli,” specifies a list of patterns that
are executed in a single execution. The example contains one PatList called
“exercise_part.” There could be several pattern lists, with the user choosing different
sets of patterns for different runs. One of the pattern lists could be a common initial-
ization sequence that several designers or test engineers use to ensure consistency
across several test programs. The PatternExec follows the PatternBurst block; it con-

to mean that it is not required to measure the output values. The next vector causes
the CLR to be released. Since the output has not been enabled, the outputs are float-
ing. However, in this example the tester is told not to measure the outputs. On the
third vecor the outputs are enabled and the expected response is listed. Notice that in
the WaveformTable the CLK signal is 0 for 25 ns and 1 for 25 ns when the WFC is a
0. Hence, this set of vectors has a period of 50 ns. It also should be mentioned that if
a signal is not specified in a vector, it retains its last value, so it was not actually nec-
essary to specify CLK = 0 in the fourth vector.
It is beyond the scope of this text to explore all of the capabilities of STIL. The
interested reader can consult the IEEE Standard P1450, which contains, in addition
to the formal specification of the STIL language, many illustrative examples. As pre-
viously pointed out, the language is intended to be independent of any specific tester
architecture. It is possible, of course, that a particular program written in STIL calls
for capabilities beyond that which a particular tester is capable of, but so long as a
tester has the capabilities called for in a particular test program, then it is the respon-
sibility of a compiler provided by that tester vendor to translate the STIL program
into a binary form acceptable to the target tester. If an IC manufacturer has several
different testers, then, in theory, at least, the same STIL test program should be able
to be ported to any of the testers simply by recompiling it. This gives the IC manu-
facturer much greater flexibility in allocating resources as products mature and
needs change.

6.4 USING THE TESTER

Digital testers are used to functionally test ICs and PCBs in order to determine
whether they respond correctly to applied stimuli. But testers can also be used to

294

AUTOMATIC TEST EQUIPMENT


strobed at the same
time. If a shared resource tester is being used, then all the OUTBUS signals would
be driven by the same wave formatter.
If a tester-per-pin tester is being used, strobe placement could be identical for
each of the signals

Q

0

–

Q

7

, like the shared resource tester, or there could be a
unique strobe placement for each signal. With its flexibility, the tester-per-pin might
be programmed to strobe all signals concurrently during one vector; then it could be
reconfigured on-the-fly to individually strobe the signals on another vector when
OUTBUS is being driven by other, unrelated signals. In some proprietary tester pro-
gramming languages, these programming instructions are called

timing sets

(TSETs).

9


specified in pin memory for the entire clock period, or they may be programmed to
apply the specified value for part of a period and apply some other value for the
remainder of that period. Some commonly used formats include return-to-comple-
ment (sometimes called surround-by-complement, or XOR), return-to-zero, return-
to-one, return-to-high-impedance, and nonreturn. Figure 6.6 illustrates nonreturn
and return-to-one waveforms. Timing generator

TG

1

is programmed to go high from
25 ns to 30 ns. Timing generator

TG

2

is programmed to go high from 15 ns to 30 ns.

Figure 6.6

Nonreturn and return-to-one waveforms.
VCC
5.0
4.0
3.0
6.0
6.5
18 ns 19 ns 20 ns 21 ns 22 ns 23 ns 24 ns

2

are identical; a logic 1 in pin memory is followed by a
logic 0, another 1, and then a 0. However, because the timing generators are differ-
ent and the waveform formats chosen are different, the resulting pin waveforms

PW

1

and

PW

2

are very different. When

PW

1

goes low, it remains low for 50 ns. When

PW
2
goes low, it remains low for 22.5 ns. The timing generators determine when the
signal changes, but the formatter determines its duration.
As mentioned earlier, complex, high-speed funcional testers are used to test ICs
and PCBs to ensure that they operate correctly. But these testers are also being used

determining which, if any, pins may represent problems during production.
When characterizing a device on an engineering test station, what happens if the
device fails to respond correctly at its intended frequency? The first thing that can
be done is to alter the clock frequency. Perhaps the device will operate correctly at a
slower frequency. If the device fails to operate correctly at any frequency, then it is
logical to assume that there is either a physical failure that occurred during the man-
ufacturing process or a design error. If several parts are available and if all of them
fail in an identical fashion, then the logical assumption is that there is a design error
that occurred during either the logic design process or the physical design process.
USING THE TESTER
297
Figure 6.7 Stretch-and-shrink test.
This will require that someone familiar with the logic investigate the response pat-
terns applied by the tester and determine where the defect is most likely to have
occurred. At some point it may be necessary to enlist the support of an E-Beam
prober to shed more light on the problem (cf. Section 6.5).
But, what happens if the device fails when running at its design frequency, but
manages to operate successfully when the clock frequency is lowered? In this case it
would be useful to know when the circuit first responds with incorrect results. This
can be done by using a stretch-and-shrink approach.
11
In this mode of operation, all
but one of the test vectors are operated at the slower clock period where the circuit
operates correctly. The first time through the vectors, the clock period for the first
vector is set to the intended design clock period. If the test passes, then the second
vector clock cycle is shrunk and the test is repeated. This is continued until eventu-
ally the test program fails. This is illustrated in Figure 6.7, where DataOut is cross-
hatched. This response may have been induced many vectors earlier by a fault that
caused some register or latch to assume an incorrect value.
With a short period on a single preceding vector, and given that the device

redesigned part. The stretch-and-shrink technique can be used to find those vectors
where the device begins to fail. That information can be used to help calibrate infor-
mation obtained from EDA tools. Conservative design rules may have resulted in a
device that is being operated far below the maximum frequency at which it is capa-
ble of operating.
A successful program for characterizing devices on an engineering workstation
requires stimuli that exercise all of the critical paths inside the device, as well as for-
matting capabilities in order to measure when signals appear at the output pins.
These are part of an AC test strategy. But a device that is plugged into a PCB affects
its environment. It may place an excessive load on other devices such that they are
unable to drive it, or it may have insufficient drive to control other devices. To guard
against this possibility, it is necessary to perform DC tests.
The DC test consists of forcing a voltage and measuring current, or forcing cur-
rent and measuring voltage. This is usually accomplished with the aid of a paramet-
ric measurement unit (PMU). It can be mechanically switched to replace a driver or
detector that is connected to a pin during normal production test operation. The
PMU can force a very precise voltage and measure the resulting current flow, or
force a very precise current and measure the resulting voltage. Measurements per-
formed during DC test include power consumption, opens and shorts, input and out-
put leakage, input and output load, and leakage.
12
When characterizing a device, it is necessary to put the device into a state that
permits the desired measurements to be made. A functional program may be run
until arriving at a desired output state. Then the measurement is taken. Alternatively,
a logic designer or test engineer may write a program whose sole purpose is to drive
the circuit into the desired state. For an output leakage test, it is necessary to put the
circuit into a state in which the outputs are tri-stated, then measure I
OZ
, the current at
an output when it is in the off-state.