T
p
w
a
c
c
P
c
v
l
v
N
a
The
D
Wir
e

T
he discret
e
simultaneo
u
p
hotovoltai
c
w
hole syste
m

m
a
s well as i
n
D
iscr
e
e
PW
M
Volta
Dipl. Ing
.
e
time contr
o
u
sly supply
o
c
applicatio
n
m
consists
o
h
ase PWM
v
n
such a wa

te Ti
m
M
In
v
g
e an
d
.
Said El-
B
a
r
o
l of a three
p
o
f three pha
s
n
with batter
y
o
f a photovo
l
v
oltage sour
c
y
so that the

o
v
erter
d
Bat
t
App
l
r
bari
CHEM
N
Depart
m
Ab
s
p
hase 4 wir
e
s
e and singl
e
y
energy st
o
l
taic array,
a
c
e inverter

ntrol
with
V
t
er
y
S
t
l
icati
o
and

N
ITZ UN
I
TECHN
O
m
ent of Ele
c
and De
r
s
tract
e
PWM inv
e
e
phase load

a
nd their rel
a
y
stems are a
d
of a
T
V
aria
b
t
ora
ge
o
n
P
rof. D
r
I
VERSIT
Y
O
LOGY
c
trical Mac
h

e
s
operation
c
y

a
ted techno
l
d
vantageous
T
hree
P
b
le D
C
e
for
P
r
. W. Hofma
n
Y
OF
h
ines
r
iable DC li
n

because th
e
P
hase
C
Lin
k
P
V
n
n

n
k voltage
fo
d
alone
d
escribed. T
h
boost conv
e
st converter
power poin
t
p
up boost
k
capacitor o
o

zed
n
ew
p
ut
u
e to
to

ation
a
nt,
p
c
i
t
e
o
c
g
t
i
a
i
d
m
I
m
p
ollution fr

sinusoidal v
a
nd load is
c
i
ntruding c
u
d
rop occurs
m
easureme
n
•
a ze
r
•
a D
C
I
n this way
t
m
odulator
o
e
e and distri
b
i
derably hig
h

u
rrent flows
t
which disto
n
ts were tak
e
r
o sequence
C
/DC conve
r
t
he symmet
r
o
f the DC/A
C
b
uted throu
g
h
.
e photovolt
a
t
ed by an ar
r
a
nt voltage

current and
r
ter is used t
r
y of the out
p
C
VSI (Volt
a
g
h the earth.
a
ic system
w
r
ay of PV p
a
f
or dc applic
from the P
V
i
ons such as
u
ch an array
u
that can ad
a
u
strated in

r
w
ith 3 phase
a
nels is dire
c
ations or in
t
V
panel. The
solar insul
a
u
nder any
w
a
pt itself to t
h
F
igure 1 this
m
um Power
P
h
ase loads o
f
t
his propose
C
link capaci

tion, tempe
r
w
eather cond
h
e changing
is provided
P
oint. The g
o
f
any art wit
h
the neutral
p
t
or bank. D
u
e
utral point
a
T
o solve thi
s
m
ented
o
ltage accor
d
a

e to load u
n
a
nd midpoi
n
s
problem t
h
d
ing to load
a
r region of
t
a
l installatio
n
o
urce invert
e
sformed, eit
h
e
s it is impo
r
n
erators var
y
oudy skies.
T
cessary to

r
tant
y

T
o
e
PV
way
a
ted
i
lter
a
ge
a
F
a
w
dSince the d
e
f
or three ph
a
a
nd extende
F

t
rol strategy
s
in [1], [2],
o
r three pha
s
current mi
n
control loo
p
s
intended s
i
f the VSI is
s
tem in the s
y

e
2 principl
e
for single p
h
[3], [5] and
s
e 4 wire V
S
n
or loop, vol

r
ibe them in
the synchr
o
d

dq0
frame.
(1)
(2)
,
t
rol method

r
was discu
s
d
beat contr
o
r
ol proposed
o
op, the D
C
c
ription of t
h
details will
o

i
s illustrate
d
n
ce estimati
o
n
d voltage a
s
imits of the
i
on (1) and
(

n
d
e
d
d
in
o
n
s

(
2)
E

F
t

quations o
n
n
ce is decou
p
r
d as seen i
n
b
y the matri
x
g
s, the dead
b

s
cribe the sy
n
e can see t
h
p
led. To en
h
n
figure 3. T
o
x
es
F
dc

,
t
or form
the
q
varia
b
r
formance o
f
and sep
a
and d
e
o
vided.
f
the curren
, b
les are cou
p
f
the contro
l

,

)

c
h othe
r
wh
e
p
acitor volt
a
m
ents
b
and
d
A
fter removi
n
e
reas
a
ge
d
are
n
g

t

T
he mathe
m
a
nd lineariz
e
f
ollow a cer
t
w
here
i
a
nd K is a c
o

v
erter must
q
o
n of the loa
v
en by ([1],
t
he target v
a
d
. The volta
g
s

o
the
0
-sceq
u
d
ed.
e
l of the DC
/
). The digit
a
c
e voltage
w
c
tor.
p
ly the load
i
mplemente
d
o
ad current i
s
o
p is constr
u
u
ence of cu

mplemente
d
n
by o
compensat
e
in figure 2,

a
nd thus the
c
s
ame manne
r
o
ltages exce
p
n
tinuos con
d
d
[11] so th
a

(8)
e
the disturb

control l
o
e
is establis
h
n
k voltage w
i
l
oad,
a
d
is
o
op
h
ed
i
ll

F
d
l
t
c
a
r
d
Figure
F

iagram.
4 inverter
c
(R
u
=
o
ws the sim
u
a
ge. The dis
t
n
of the PW
M
i
lter is also
d
I
t shows the
Ω
, R
w
=200
0
m
. This show
r
bance of th
e

u
=
R
s the high d
y
e
output volt
e
sult of the
c
capacitor v
o
w
=2000
Ω

)

a
t
s of the dea
e
inverter c
u
r
due to loa
d
g
ure 5 show
s

t
output filte
r
w
=2000Ω )
a
o
rmance of
t
k
ly compens
a
dc link volt
a
e
output filt
e
o
lled DC li
n
o
l for unbal
a
r
when the c
o
s
. As a resul
t
t

, the capaci
t
w
hen the D
C
o
ad changes
b
y an arrow
e
d dead bea
t
s
tortion of t
h
a
ted in the r
i
a
lanced loa
d
w
ith uncontr
o
l
s exceed th
e
t
or voltage
o

l
tage
b

Figure
5

5
capacitor
v

v
oltage of the output fil
t
v
o
t
er with unb
o
ltage

alanced loa
d
d
and contr
o
o
lled DC li
n


[8] Atsuo Kawamura, Toshimasa Haneyoshi and Richard G. Hoft, "Deadbeat Controlled PWM
Inverter with Parameter Estimation Using Only Voltage Sensor", IEEE Transactions on Power
Electronics, Vol. 3, No. 2, April 1988, pp. 118-125.
[9] P. R. K. Chetty "Current Injected Equivalent Circuit Approach to Modeling and Analysis of
Current Programmed Switching DC-DC Converters (Discontinuous Inductor Conduction Mode)",
IEEE Transactions on Industrial Applications, Vol. IA-18, No. 3, May/June 1982, pp. 295-299.
[10] Francisco Guinjoan, Javier Calvente, Alberto Poveda and Luis Martinez, "Large-Signal
Modeling and Simulation of Switching DC-DC Converter", IEEE Transactions on Power
Electronics, Vol. 12, No. 3, May 1997, pp. 485-494.
[11] F. Al-Hosini, ABB Corporate Research, Sweden, "An Aproximate Dead-Beat Control
stratigy for the disign of functions regulators in DC/DC Converters", EPE Trondheim 1997, Vol. 3,
pp. 155-160.