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9.3 Conditional Compilation and Execution
A portion of Verilog might be suitable for one environment but not for another. The
designer does not wish to create two versions of Verilog design for the two environments.
Instead, the designer can specify that the particular portion of the code be compiled only
if a certain flag is set. This is called conditional compilation.
A designer might also want to execute certain parts of the Verilog design only when a
flag is set at run time. This is called conditional execution.
9.3.1 Conditional Compilation
Conditional compilation can be accomplished by using compiler directives `ifdef, `ifndef,
`else, `elsif, and `endif. Example 9-5
contains Verilog source code to be compiled
conditionally.
Example 9-5 Conditional Compilation
//Conditional Compilation
//Example 1
'ifdef TEST //compile module test only if text macro TEST is defined
module test; endmodule
'else //compile the module stimulus as default
module stimulus; endmodule
'endif //completion of 'ifdef directive

//Example 2
module top;

can be used only for behavioral statements. The system task keyword $test$plusargs is
used for conditional execution.
Consider Example 9-6
, which illustrates conditional execution with $test$plusargs.
Example 9-6 Conditional Execution with $test$plusargs
//Conditional execution
module test; initial
begin
if($test$plusargs("DISPLAY_VAR"))
$display("Display = %b ", {a,b,c} ); //display only if flag is set
else
//Conditional execution
$display("No Display"); //otherwise no display
end
endmodule
The variables are displayed only if the flag DISPLAY_VAR is set at run time. Flags can
be set at run time by specifying the option +DISPLAY_VAR at run time.
Conditional execution can be further controlled by using the system task keyword
$value$plusargs. This system task allows testing for arguments to an invocation option.
$value$plusargs returns a 0 if a matching invocation was not found and non-zero if a
matching option was found. Example 9-7
shows an example of $value$plusargs.
Example 9-7 Conditional Execution with $value$plusargs
//Conditional execution with $value$plusargs
module test;
reg [8*128-1:0] test_string;
integer clk_period;

using a different time unit, e.g. 100 ns. Verilog HDL allows the reference time unit for
modules to be specified with the `timescale compiler directive.
Usage: `timescale <reference_time_unit> / <time_precision>
The <reference_time_unit> specifies the unit of measurement for times and delays. The
<time_precision> specifies the precision to which the delays are rounded off during
simulation. Only 1, 10, and 100 are valid integers for specifying time unit and time
precision. Consider the two modules, dummy1 and dummy2, in Example 9-8
.
Example 9-8 Time Scales
//Define a time scale for the module dummy1
//Reference time unit is 100 nanoseconds and precision is 1 ns
`timescale 100 ns / 1 ns

module dummy1;

reg toggle;

//initialize toggle
initial
toggle = 1'b0;

//Flip the toggle register every 5 time units
//In this module 5 time units = 500 ns = .5 ms
always #5
begin
toggle = ~toggle;
$display("%d , In %m toggle = %b ", $time, toggle);
end

endmodule

15 , In dummy1 toggle = 1
20 , In dummy1 toggle = 0
25 , In dummy1 toggle = 1
30 , In dummy1 toggle = 0
35 , In dummy1 toggle = 1
40 , In dummy1 toggle = 0
45 , In dummy1 toggle = 1
> 5 , In dummy2 toggle = 1
50 , In dummy1 toggle = 0
55 , In dummy1 toggle = 1
N
otice that the $display statement in dummy2 executes once for every ten $display
statements in dummy1.
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