Part III
Baseband Technology
‘Software runs on Silicon’ – and in the case of SDRs today, the competition between
approaches and technologies for exponentially increasing baseband processing requirements
is proving a fertile ground for innovation, in both conceptual approaches and implementation
architectures.
Software Defined Radio
Edited by Walter Tuttlebee
Copyright q 2002 John Wiley & Sons, Ltd
ISBNs: 0-470-84318-7 (Hardback); 0-470-84600-3 (Electronic)
7
Baseband Processing for SDR
David Lund
a
and Bahram Honary
b
a
HW Communications Ltd.
b
Lancaster University
Many technologies require substantial research and development to facilitate the emergence
of mature and generic software defined radio architectures, as will be evident from a perusal
of the contents of this volume or the other literature in the field. Our own chapter focuses upon
the broad ranging topic of baseband processing, an important and central element of such
architectures. Alongside networking of these enhanced capability and flexible systems, the
radio frequency processing aspects of the physical layer are required to accommodate a
flexible range of different frequencies, formats, and environments. Baseband processing is
perhaps one of the most potentially fruitful areas of development anticipated over the next
few years – indeed, significant progress is already evident.
7.1 The Role of Baseband Architectures
The baseband of any radio system is responsible for digitally transforming raw data streams

level of service as the users’ application requires.
Research in SDR commonly takes a top down approach. Evaluation of the market looks at
what the user requires in terms of application. Network developers look at how to provide
such applications and services to the user. Equipment developers develop and use compo-
nents to build the infrastructure needed to implement the networks and terminals.
Equipment developers will frequently take predominantly off-the-shelf component tech-
nologies and, maybe after some specific modification, integrate them into infrastructure
equipment. This is certainly how second-generation mobile equipment has been developed,
with GSM terminals commonly containing hybrid application specific integrated circuit
(ASIC) devices based upon a particular microprocessor (mP) or digital signal processor
(DSP) core.
New component technologies are rapidly emerging which complement the now traditional
mP and DSP technologies. Field programmable gate array (FPGA) and new reconfigurable
fabric processors give an alternative edge to the use of aging mP and DSP technologies.
The remainder of this chapter describes a range of technologies and techniques presently
available for implementation of the baseband processing subsystem. The concept of flexible
processing is introduced to describe the higher level problems associated with using such
technology. The status of currently available component technologies is described, illustrat-
ing the wide range of processing resource already available today. These are presented to
developers of SDR-based equipment, providing insights into how they may be used for
different algorithmic purpose.
The introduction of new processing technologies also requires development of new design
tools and methods. The status of such tools is also described with discussion of requirements
not only for initial design of an SDR system but also its maintenance. A discussion of object-
oriented methods illustrates how the high level software developer may be given the neces-
sary visibility and understanding of the processing resources available. With such visibility,
SDR operators and maintainers can then allocate the necessary time critical baseband proces-
sing chains to a multitude of processing resources with maximum efficiency.
7.2 Software Radio – From Silicon to Software
It is important here to recognize the context within which, for the purposes of this chapter, we

pioneered by researchers in computer-based fixed networks. As third-generation mobile
networks are developing, the concept of QoS is emerging as an important requirement for
provision of a wide range of high quality data services to the mobile user.
Network management is also a hot topic in the quest for improving the mobile and Internet
experience. Providing efficiency in the system along with network management allows easy
deployment and control of systems and hence efficient service to the user. Second-generation
mobile networks consist of mobile terminals, base stations, and switching centers. Third-
generation networks provide much more functionality in order to improve user services.
Various domains and strata providing different levels of data access and control are defined,
allowing the capability to provide advanced, user specific services across a broad range of
environments and across multiple networks [1]. Network management of these, already
multimode, systems is proving to be a huge task. The concept of software radio and the
advent of reconfigurable processing systems makes the organization and management of the
network even more complex, as the majority of functionality in the network becomes capable
of being modified with only the actual hardware architecture remaining static.
The CAST
3
project illustrates the need for advanced management methods by focusing on
Baseband Processing for SDR 203
1
A similar distinction, using the terms ‘software signal processing’ and ‘software control’, is made and explained
further in Chapter 1.
2
For an overview of such research in Europe see Dillinger and Bourse in Software Defined Radio: Origins, Drivers
and International Perspectives’, Tuttlebee, W. (Ed.), John Wiley & Sons, Chichester, 2002, Chapter 7.
3
Configurable radio with Advanced Software Technologies (CAST) project is European Commission Information
Society Technologies (IST) funded Project, IST-1999-10287. HW Communications Ltd are primary contractors in
this project, within which the authors of this chapter actively participate.
the use of organic intelligence to cope with the enormous range of situations and scenarios

natives proposed today as possible baseband technology solutions.
1. Baseband component technologies
– dynamic capability – how flexible are different processing devices?
– processing capability – how powerful are different processing devices?
– physical constraints – what are their physical limitations?
2. Design tools and methods
– standardized tools and methods – global compatibility and coherence.
– specification tools and methods – transferral of design information.
– mixed mode capability – mixed component technologies imply the need for mixed tool
environments.
– tool processing requirements – can a highly complex system be simulated?
– compliance to design procedures – design flows for different technologies and combi-
nations.
– algorithm processing requirements – to provide enhanced automated design decisions.
– automated hardware selection for algorithms – also for automated design decisions.
– system simulation and emulation – testing methods at different levels.
3. System maintenance
– object oriented system control – control of low level processing resource by higher
layer distributed control.
– configuration and reconfiguration mechanisms – controlling the physical processing
resources.
– initial set up and configuration – how is a system initialized?
– automatic intelligent decisions – higher capability requires more complex decisions.
– capability classification – knowledge of the processing system is required for in-system
decision making.
– resource allocation – efficiently allocating functions to processing resources.
– configuration update procedures – methods of securely controlling and updating dyna-
mically distributed systems.
It is evident that the advances in silicon technology today are outstanding and provide huge
capabilities. However, in order to use these technologies efficiently, more development is

efficient processing systems. Each processing algorithm has a different combination and set
of discrete operations. The combination of logic operations, adds, subtracts, multiplies,
divides and condition operations is different for each algorithm. The first digital signal
processors (DSP) were optimized mainly for the huge demand of pipelined multiply accu-
mulate (MAC) operations which form the basis of most discrete signal processing algorithms.
Software Defined Radio: Enabling Technologies206
Figure 7.2 The breadth of enabling technology required to support SDR
Figure 7.3 illustrates how the FPGA can provide a solution for systems requiring both high
performance and a high degree of function capability. At one extreme, hardwired devices,
such as an ASIC, can only perform a limited function; they do, however, provide a very high
performance. The DSP, being software programmable, can offer an almost unlimited function
capability, but, of course, the serial processing nature of traditional DSPs does limit perfor-
mance.
Figure 7.4 illustrates how the FPGAs processing resource is able to provide this combi-
nation of high function with high dynamic capability. Any processing algorithm can be
decomposed into subelements which incrementally carry out the computation required by
the algorithm. Each of these subelements has dependencies upon the data available as a
result of other subelements’ processing. In Figure 7.4, subelement 2 is dependant upon 1
and subelement 4 is dependant upon 3. Subelement 5 is dependant upon the result of 2 and
4. A single mP or DSP software based computation of the algorithm must process each sub-
element sequentially, satisfying the dependencies, i.e. 1 ) 2 ) 3 ) 4 ) 5or3) 4 ) 1 )
2 ) 5. Improved performance may be gained by using multiple processors to compute 1 )
2 and 3 ) 4 in parallel. Multiple processors do, however, result in higher power consump-
tion and the requirement for more silicon area. The FPGA processing resource is fine
grained and can carry out this parallelism to a degree as small as individual logic gate
operations.
An important trade-off here is ease of implementation vs. performance. An FPGA circuit
with currently available design tools is more difficult to configure than the well-established
programming methods of the DSP. A small price is also paid in time when reconfiguring.
Reconfiguring FPGA logic is much slower than a simple function call in the mP or DSP.

in a single DSP clock cycle; indeed, high performance DSPs may even support two or more
MACs per clock cycle.
Addressing modes are also optimized in DSP architectures, allowing efficient loading and
Software Defined Radio: Enabling Technologies208
4
The newsgroup comp.dsp provides a thorough working analysis of DSPs from which some of this historical and
tutorial material is sourced.
Figure 7.4 Comparison between software and reconfigurable logic
storage of discrete data to and from memory circuits. Data access is also improved by using
Harvard architectures to allow the DSP to access both data and instructions simultaneously.
Functions such as pre/post addressing registers (pointers) store addresses of locations of
discrete data. They often also incorporate their own arithmetic function to allow for fast
update of the pointer to quickly address the next required data element. Circular addressing is
also common, allowing a pointer to rotate around a defined area of memory to provide a
cycle-based memory access. Along with the MAC, the DSP may also provide execution
Baseband Processing for SDR 209
Table 7.1 A comparison of DSP engines
Device Manufacturer Clock
(MHz)
Performance Precision Optimized for
DSP56800 Motorola 80 40 MIPS 16 bit fixed Control applications
(peripheral IO)
DSP56600 Motorola 60 60 MIPS 16 bit fixed Cell phone and 2-way
radio
DSP56367 Motorola 150 150 MIPS 24 bit fixed Audio processing
MSC8102
(Starcore)
Motorola 300 4800 MMAC 16 bit fixed High processing
performance
ADSP-2191 Analog

consumption 0.05 mW/
MIPS
TMS320C62x Texas
Instruments
150–300 1200–2400
MIPS
Fixed Fixed point processing
power
TMS320C64x Texas
Instruments
400–600 3200–4800
MIPS
Fixed Fixed point processing
power
TMS320C67x Texas
Instruments
100–167 600–1000
MFLOPS
floating Floating point
processing power
TMS320C8x Texas
Instruments
50 100
MFLOPS
equiv
32 bit fixed Telecommunications
and image parallel
processing
2 BOPS
(RISC)

faces in the context of the user;
† power consumption – to allow usage in an increasing range of portable battery-powered
consumer (and other) devices;
† performance range – providing ranges of processing performance with differing MIPS and
MFLOPS to provide the best cost vs. performance trade-off for specific processing require-
ments.
7.3.2. Field Programmable Gate Arrays
The field programmable gate array (FPGA) was first introduced by Xilinx Inc in 1985 [42].
Since then the technology has been enhanced and developed with relatively little interest in
its dynamic capability. The major application of FPGAs has traditionally been as a low cost
alternative to the design of application specific integrated circuits (ASIC), particularly for low
volume applications. A brief history and a description of many applications of the devices can
be found in [14].
At present there are many different vendors who provide FPGA devices, hybrid variations,
and tools, including those listed below. Some of these suppliers represent long established
Software Defined Radio: Enabling Technologies210
companies, while others are relative newcomers and start-ups who have sought to bring
innovative technology approaches. Many of these already go beyond the limitations of
traditional FPGAs, DSPs, and/or ASICs, specifically to address the emerging software
radio market opportunity.
† Altera
† Atmel
† Cypress
† Fast Analog Solutions Ltd
† Gatefield
† Lattice
† Lucent Technologies
† Motorola
† QuickLogic
† Xilinx

tures, although still relatively fast, pay the performance price arising from the extra routing
required to interconnect them. The trade-off for performance is, of course, flexibility. Fine-
grained architectures are more flexible than coarse-grained due to the greater possibilities
provided by a high quantity of simple logic. Coarse-grained, however, are limited to the
specific optimized functions. To illustrate in more detail the features of the fine- and coarse-
grained FPGA architectures, we describe the Xilinx Virtex and Altera APEX device
families.
7.3.2.1 The Xilinx Virtex Architecture
The Xilinx Virtex architecture [42] follows the classic FPGA architecture as illustrated in
Figure 7.5 but features several coarse-grained enhancements. The architecture consists of a
standard array of CLBs with a partial border of block RAMS (BRAMs). The periphery of the
chip consists of configurable I/O blocks (IOBs), which are capable of interfacing to the
outside world via a multitude of voltages and signalling schemes. The delay locked loop
(DLL), as supplied by most modern FPGAs, provides correction of clock skew on and off
chip, ensuring that all logic is correctly synchronized. The most interesting part of the Virtex
FPGA is its extremely versatile CLB architecture.
The Virtex CLB is split into two halves (slices). Each slice has two distinct data paths, each
comprising:
† a look up table (LUT), which can perform (at least) three possible functions
– 4 input, 1 output look up table, for definition of logic functions.
– 16 deep by 1-bit wide RAM or ROM
– 16-bit shift register
† control, which can be used for
– combining both LUTs to create larger logic functions
– combining both LUTs to provide larger RAMs or a dual port capability
– arithmetic support for high speed multipliers
Software Defined Radio: Enabling Technologies212
– carry control for adders/subtractors
– route through for more flexible routing
† Configurable storage element, which can support:

† content addressable random access memory (CAM)
Clock distribution is achieved by use of phase locked loops which can distribute clocks and
their multiples with minimal skew. The device supports most recognized I/O and interfacing
standards. The maximum equivalent gate count of the APEX at this time is 2.5 million with a
maximum of 432 kbits of on-chip RAM. Configuration is achieved serially and only config-
uration of the full device is possible.
Baseband Processing for SDR 213
7.3.3 Recent Digital Developments
The advent of field programmable technology, coupled with the drive to provide solutions for
the third-generation mobile, has recently sparked an interest in providing ASICs with either
more specific functionality or a greater variation in available resources.
Motorola, Analog Devices, Texas Instruments, and various others provide their DSP cores
with other silicon intellectual property (IP) for specific communication solutions. At this time
there is a major focus on providing solutions for asynchronous digital subscriber line (ADSL)
modems and other remote access (RAS) devices.
Some specific solutions provide so-called ‘communications processors’. These devices
split the ASIC or chipset architecture into the OSI layers and provide a range of service at
each layer. This architecture provides the signal chain of processing required for the structure
of baseband processing as described by [27]. The following examples illustrate a convergence
between devices of fine- and coarse-grained FPGA resource, and silicon IP cores.
7.3.3.1 Quicklogic
Quicklogic provides a range of devices which allows combinations of different processing
resources dependant upon the requirements of the processing application. The concept of
‘embedded standard products (ESP)’ describes how different IP processing functionality can
be brought together on a single IC.
Four distinct types of resource are provided:
† data I/O – low voltage differential signaling (LVDS), PCI, fiber channel
† array of logic cells (LC) – the Quicklogic version of fine-grained CLB
† dual port RAMs (DPRAM) – providing dedicated coarse-grained memory resource
† embedded computation units (ECU) – dedicated coarse-grained arithmetic processing,

The most noticeable addition is the dedicated multiplier resource. Multipliers of this size have
always been a challenge to implement using, fine-grained field programmable resource. The
addition of these coarse-grained units will improve the MAC ability but may also increase
redundancy for applications which do not need them.
The largest Virtex-II device includes:
† CLB array – 128 £ 120
† 18 £ 18 multipliers – 192
† 18-kbit BRAMS – 192
7.3.4 Reconfigurable Analog Components
Two major problems which drove the evolution from analog to digital processing were the
requirements of improved flexibility and stability. Analog processing, even when IC-based,
relies upon fixed quantities of capacitance, resistance, and inductance, traditionally imple-
mented using fixed, soldered discrete components. Flexibility is therefore impractical without
changing the physical components. Recent attempts have been made to provide IC-based
solutions which house a choice of analog components to facilitate adaptive analog integrated
circuitry. These devices are commonly described as field programmable analog arrays
(FPAA).
The FPAA, similar to the FPGA, consists of an array of configurable analog blocks (CAB).
These provide an analog processing resource surrounded by configurable routing. A CAB and
its support circuitry may consist of operational amplifiers with connections to components
required for configuring analog filters, summing amplifiers, oscillators, rectifiers, compara-
tors, and virtually any other type of analog circuit.
The Anadigm AN10E40 [4] is the most interesting device available at present which
illustrates that the traditional problems associated with stability are being brought under
control. The CABs used in the Anadigm device consists of op-amps and switched capacitor
circuitry which ensures that voltage drift due to temperature variation and aging is almost
Baseband Processing for SDR 215
eliminated. Almost all circuits which can be constructed from an op-amp with discrete
components can be achieved in a AN10E40 CAB. The AN10E40 consists of a 4 £ 5 array
of CABs surrounded by routing, I/O, spare op-amps, voltage reference generation, and

investment targeted at particular optimizations.
The ultimate in both flexibility and performance is clearly the finest-grained field program-
mable architectures. Such architectures can ultimately provide any function, or combination
of functions, consuming minimal extra silicon area in comparison to the full custom ASIC
solution. In this respect the Virtex CLB architecture would appear to be arguably the most
flexible.
If we consider the full set of all classes of processing we must include all generic comput-
ing, communication, and control systems – communications only forms a subset. By taking a
closer look at the communication system itself, the processing requirements may be seem to
include a subset of functions specific only to the communications application. Modulation,
channel coding, multiple access, etc. are such examples. Looking even further into each class
Software Defined Radio: Enabling Technologies216
of communication function an array of different processing algorithms is available; e.g. the
modulation function subset includes BPSK, QPSK, GMSK, QAM, etc. These can be consid-
ered as leaf classes for now, but even these can be broken down further to give specific
algorithms providing different levels of algorithmic gain. If the full system is broken down
into all possible leaf classes, it is quite clear that, although some have quirky features,
commonalities in processing requirements can be identified.
5
For example, certain classes
of demodulator consist mainly of filters requiring extensive MAC capability from the hard-
ware. High performance Turbo decoding functions require high levels of precision, often
requiring floating point operations.
When choosing resources for any processing system, careful matching of hardware to
algorithm is required for ultimate efficiency. Availability does, however, restrict the choice
at the present time. For the medium term development of software defined radio it is expected
that devices will appear incorporating a combination of the functionalities available today in
the separate technologies described above, optimized according to the required functionality.
In the long term, when consideration for cognitive radio and ad hoc networks implies very
comprehensive functionality, the fine-grained architecture should provide the most efficient

5
This approach of parameterization, and its potential role, is described in Chapter 8 by Friedrich Jondral.
The development of tools and methods is generally much slower than the advances in new
component technologies. Some vendors design silicon with tools and methods in mind, but
many only produce relatively basic tool support. The development of advanced tools and
methods generally relies upon third parties. As devices become more complex, the learning
curve of the third party becomes more difficult to conquer. This results in much slower
provision of support for those devices which provide the most efficient solution to the specific
processing problem at hand. For this reason a system designer will sometimes trade off
efficiency for ease of design and implementation, resulting in the choice of processing
architecture based less on performance and more on its supporting tools.
7.4.1 Design Tool Concepts – an Analogy
The first silicon microprocessors (mP) required definition of their computation using machine
code. This hardware specific method was termed the first generation of programming
languages. Binary sequences defined the data and instructions of these early devices.
The second generation saw the introduction of assembly languages. Although still device
specific, this provided a short hand form for defining the binary machine code. The assembly
code, however, still relied on a computer to convert from the assembly to the machine code.
The first assembler tools had themselves to be defined in machine code. This was the first
monumental advancement of design tools for computation.
Third-generation tools included more structured approaches to defining computation.
Languages such as ANSI C, Pascal, and many more provide facilities for easy definition
of program flow and data storage.
Fouth-generation languages added to the third by providing application specific function-
ality. Structured query language (SQL), for example, provides a language for defining
computation based upon complex databases.
The most interesting combination of third- and fourth-generation languages are those
which provide object oriented (OO) processing. OO is fairly application generic and provides
an interpretation of processing systems as if they had been built from real objects. Although
these objects only exist in a virtual world, the human mind can understand clearly how these

function is defined, layout engineers are responsible for ensuring the design is efficiently
placed on the silicon substrate ready for manufacture, again relying on electronic tools.
Throughout this entire flow the design remains a digital representation, stored on compu-
ters. Portions of design are passed from engineer to engineer in digital form. Each different
stage requires its own set of design tools for manipulation of the digital model which repre-
sents the design. Such engineering design automation (EDA) tools also require EDA engi-
neers to aid the design flow and ensure that design data flows easily between design engineers
and the different tools.
The following is a list of typical tools which may be required at different levels of this
design flow:
† design entry – schematic or hardware description language (HDL) for input of the design
to the computer
† synthesis – synthesizing logic or circuit from a HDL description
† layout – using physical silicon knowledge to automatically place library components and
connect them together based on knowledge of the design requirements
† timing analysis – analysis of propagation times of electrical signals through the circuit and
routing
† library management – definition and management of library components for use by logic
and layout designers and the associated automated tools
† power analysis – analyzing the power consumption in the laid-out design
† simulation – at all design stages the design function must be verified. Many test simula-
tions will stress the design to ensure its validity
† package design – automated method to ensure the optimum placement of the silicon die
into its package with I/O pins
† design rules checking (DRC) – at all stages the DRC checks validity of the design based
upon a rule set. The rule set generally ensures overall correctness and compatibility with
other design tools and, more importantly, the silicon manufacture process
† touch up editors and tools – automated tools are never perfect and often add inefficiency to
the design or in some extreme cases even compromise the design. EDA tools are so
Baseband Processing for SDR 219

uration of the FPGA. This basic level of using the FPGA targets the huge market of ASIC
replacement. The concept of ASIC replacement addresses applications for which the perfor-
mance of the FPGA is sufficiently powerful to avoid the need for the costly design of a
dedicated ASIC. Although efficient use of the FPGA still requires experience and expertise,
the capability of configuring and testing immediately on the bench is possible. The cost, in
money and time, of multiple silicon fabrication iterations is thereby avoided. The ASIC
replacement business far exceeds the market for reconfigurable processing at present; there-
fore the development of tools for this purpose has been limited.
A similar prediction can be made for the future evolution of FPGA design tools as that
relating to the DSP. Figure 7.7 illustrates this prediction. Basic tools are now available with
extensive development in IP cores. Tools for supporting the reconfigurable nature of FPGA
are emerging [18]. The HW2000 [15] development system allows use of partially reconfigur-
able Xilinx Virtex FPGA along with cross point devices for dynamic data flow manipulation
between the processing devices.
7.4.4 Future Design Flows and Tools
Recognizing the key impact that availability of suitable tools plays in design choices, some
manufacturers of new SDR-targeted processing devices are developing these with good
consideration for the design tools. The Chameleon RCP is an example of one such device
which has been designed with forward thought for its design tools.
Some system level tools are already supporting ‘push button’ FPGA design flows. These
are, however, static and still only consider one time configuration. The status of design tools
for individual component technologies is known. Software defined radio systems, however,
require a combination of the different types of processing resource. In many cases there are
few design tools and methods yet defined for such purposes. These systems require careful
Baseband Processing for SDR 221
Figure 7.7 Predicted evolution of FPGA design tools focused towards reconfigurable processing
consideration of the interaction between devices and their related functions as they change in
time.
In order to carry out efficient design and implementation of any piece of hardware and/or
software, design flows are essential in defining how a particular product development may

effectively verify that reconfiguration between modes is possible. Once the data flow is
verified, the individual functions may be implemented towards their chosen hardware plat-
form and verified by individual simulation. Once the functions are integrated into the final
system, co-simulation may be required and then hardware verification can complete the
implementation.
The example in Figure 7.8 of a design flow of a fairly application specific SDR system
illustrates the complexities, compared to static systems. Dedicated design tools simply do not
yet exist for many of the stages in the above design flow. Some existing tools may be modified
but at the expense of design time. This present situation represents both a need and a market
opportunity.
7.5 System Design and Maintenance
Many traditional design flows and methodologies have evolved to incorporate system main-
tenance and redesign as an integral part of the design life cycle. The life cycle of reconfigur-
able systems is set to rotate more slowly as it evolves. Asymptotically, this cycle would freeze
in the redesign stage and become a stage of pure maintenance. This perfect stage in the
evolution of reconfigurable systems should consist of hardware platforms whereby the only
redesign and maintenance will be in the software or function definition.
6
7.5.1 Object Orientation
Object-oriented approaches are the most logical of methods for the design and maintenance
of reconfigurable systems, for the reasons outlined below. An object consists of a description
of a processing entity, comprising attributes and methods. Attributes describe the object in
terms of constant or variable parameters; methods describe actions which can be executed to
manipulate the object in some way. For example, an icon shortcut on the desktop of a
Windows-based PC can be considered as an object. Its attributes include:
† graphic – the image which represents the icon.
† text – the description text usually placed underneath the icon
† executable – the program to execute when the icon is double clicked
Its methods include:
† execute_on_double_click – execute the application represented by the executable attribute

syntactical representation of objects by programmers. C11, Java, and many other program-
ming languages allow definition of classes and objects and their interaction within the
computer environment. Distributed languages are now evolving which allow remote control
of objects over networks. Systems such as CORBA and Java RMI incorporate methods for
brokering, distribution, and remote invocation of objects and their methods as distributed
around networks.
Networks of processing resource can be dynamically allocated using well-known resource
allocation methods. Each processing node in the network requires run-time support for the
manipulation of objects. This support may provide information such as system status and
loading, allowing effective control of object distribution and data flow. Many of these meth-
ods consider processing resource as a particular node which can be loaded with processing
objects as and when required. The definition of the node is commonly associated with a single
processing entity, commonly consisting of either a standalone PC or a card incorporating a
processor with the necessary support functions. Such distributed systems are commonly
found in mobile base stations and data routers.
7.5.2 Distributed Resource Management in SDR Processors
Reconfigurable signal processing systems such as SDR must have access to distributed
methods to allow control and maintenance of processing. Processing must be dynamic in
these systems and capable of being controlled remotely for cases of wireless networks. The
Software Defined Radio: Enabling Technologies224