Lecture 4:
Nonideal
Transistor
Theory
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 2
Outline
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
 Process and Environmental Variations
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 3
Ideal Transistor I-V
 Shockley long-channel transistor models
( )
2
cutoff
linear

CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 4
Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, V
DD
= 1.0 V
0
0.2
0.4
0.6
0.8 1
0
200
400
600
800
1000
1200
V
ds
I
ds
(µA)
V
gs
= 1.0
V
gs
= 1.0

Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with V
gs
Velocity saturation & Mobility degradation:
I
on
lower than ideal model predicts
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 5
ON and OFF Current
 I
on
= I
ds
@ V
gs
= V
ds
= V
DD
– Saturation
 I
off
= I
ds
@ V
gs
= 0, V

I
on
= 747 mA @
V
gs
= V
ds
= V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 6
Electric Fields Effects
 Vertical electric field: E
vert
= V
gs
/ t
ox
– Attracts carriers into channel
– Long channel: Q
channel
∝ E
vert
 Lateral electric field: E
lat
= V
ds
/ L
– Accelerates carriers from drain to source

 High E
vert
effectively reduces mobility
– Collisions with oxide interface
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 9
Velocity Saturation
 At high E
lat
, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches v
sat
• Electrons: 10
7
cm/s
• Holes: 8 x 10
6
cm/s
– Better model
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 10
Vel Sat I-V Effects
 Ideal transistor ON current increases with V
DD
2
 Velocity-saturated ON current increases with V
DD

α-Power Model
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
VV
V
I I VV
V
I VV

<


= <



>

( )
( )
/2
2
dsat c gs t
dsat v gs t

p
GateSource Drain
bulk Si
n
+
V
DD
GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 13
Chan Length Mod I-V
 λ = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
( )
( )
2
1
2
ds gs t ds

s
or decreasing V
b
increases V
t
 φ
s
= surface potential at threshold
– Depends on doping level N
A
– And intrinsic carrier concentration n
i
 γ = body effect coefficient
( )
0t t s sb s
VV V
γφ φ
=+ +−
2 ln
A
sT
i
N
v
n
φ
=
si
ox
si

η
t t ds
VV V
η
′
= −
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 18
Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes V
t
a function of channel length
 Short channel effect: V
t
increases with L
– Some processes exhibit a reverse short channel
effect in which V
t
decreases with L
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 19
Leakage
 What about current in cutoff?
 Simulated results

gs t ds sb
ds
TT
V V V kV
V
nv v
ds ds
II
γ
η
−+ −
−

= −



CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 22
Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to t
ox
and V
DD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (t

– And area and perimeter of diffusion regions
– Typically < 1 fA/µm
2
(negligible)
e1
D
T
V
v
DS
II

= −



CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 25
Band-to-Band Tunneling
 Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase V
t
 Increases junction leakage to significant levels
– X
j
: sidewall junction depth
– E
g