Chapter 1.
Ex. 1. Consider two different implementations, M1 and M2, of the same instruction set. There are
three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 80
MHz and M2 has a clock rate of 100 MHz. The average number of cycles for each instruction
class and their frequencies (for a typical program) are as follows:

a) Calculate the average CPI for each machine, M1, and M2.
b) Calculate the average MIPS ratings for each machine, M1 and M2.
c) Which machine has a smaller MIPS rating ? Which individual instruction class CPI do you
need to change, and by how much, to have this machine have the same or better
performance as the machine with the higher MIPS rating (you can only change the CPI for
one of the instruction classes on the slower machine)?
Ex. 2. (Amdahl’s law question) Suppose you have a machine which executes a program consisting
of 50% floating point multiply, 20% floating point divide, and the remaining 30% are from
other instructions.
a) Management wants the machine to run 4 times faster. You can make the divide run at most
3 times faster and the multiply run at most 8 times faster. Can you meet management’s goal
by making only one improvement, and which one?
b) Dogbert has now taken over the company removing all the previous managers. If you make
both the multiply and divide improvements, what is the speed of the improved machine
relative to the original machine?
Ex. 3. Suppose that we can improve the floating point instruction performance of machine by a
factor of 15 (the same floating point instructions run 15 times faster on this new machine).
What percent of the instructions must be floating point to achieve a Speedup of at least 4?
Ex. 4. Just like we defined MIPS rating, we can also define something called the MFLOPS rating
which stands for Millions of Floating Point operations per Second. If Machine A has a higher
MIPS rating than that of Machine B, then does Machine A necessarily have a higher MFLOPS
rating in comparison to Machine B? Note: MIPS rating is defined by: MIPS = (Clock
Rate)/(CPI * 10
6
)

non-pipelined implementation. Here are some design parameters for the two possibilities:
Parameter
Pipelined Version
Non-pipelined Version
Clock Rate
500MHz
350MHz
CPI for ALU instructions
1
1
CPI for Control instructions
2
1
CPI for Memory Instructions
2.7
1
a) For a program with 20% ALU instructions, 10% control instructions and 75% memory
instructions, which design will be faster? Give a quantitative CPI average for each case.
b) For a program with 80% ALU instructions, 10% control instructions and 10% memory
instructions, which design will be faster? Give a quantitative CPI average for each case.
Ex. 10. A designer wants to improve the overall performance of a given machine with respect to a
target benchmark suite and is considering an enhancement X that applies to 50% of the
original dynamically-executed instructions, and speeds each of them up by a factor of 3. The
designer’s manager has some concerns about the complexity and the cost-effectiveness of X
and suggests that the designer should consider an alternative enhancement Y. Enhancement
Y, if applied only to some (as yet unknown) fraction of the original dynamically-executed
instructions, would make them only 75% faster. Determine what percentage of all
dynamically-executed instructions should be optimized using enhancement Y in order to
achieve the same overall speedup as obtained using enhancement X.
Ex. 11. Prior to the early 1980s, machines were built with more and more complex instruction set.

This machine has no delay slots. The stack grows downward (toward lower memory addresses).
The following registers are used in the calling convention:

Ex. 16. In the snippet of MIPS assembler code below, how many times is instruction memory
accessed? How many times is data memory accessed? (Count only accesses to memory, not
registers.)
lw $v1, 0($a0)
addi $v0, $v0, 1
sw $v1, 0($a1)
addi $a0, $a0, 1
Ex. 17. Use the register and memory values in the table below for the next questions. Assume a 32-
bit machine. Assume each of the following questions starts from the table values; that is, DO
NOT use value changes from one question as propagating into future parts of the question.

a) Give the values of R1, R2, and R3 after this instruction: add R3, R2, R1
b) What values will be in R1 and R3 after this instruction is executed: load R3, 12(R1)
c) What values will be in the registers after this instruction is executed: addi R2, R3, #16
Ex. 18. Loop Unrolling and Fibonacci: Consider the following pseudo-C code to compute the fifth
Fibonacci number (F(5)).
1 int a,b,i,t;
2 a=b=1; /* Set a and b to F(2) and F(1) respectively */
3 for(i=0;i<2;i++)
4 {
5 t=a; /* save F(n-1) to a temporary location */
6 a+=b; /* F(n) = F(n-1) + F(n-2) */
7 b=t; /* set b to F(n-1) */
8 }
One observation that a compiler might make is that the loop construction is somewhat unnecessary.
Since the the range of the loop indices is fixed, one can unroll the loop by simply writing three
iterations of the loop one after the other without the intervening increment/comparison on i. For

execute the instruction).

Do the following: Write the MIPS assembly code to implement a block copy without this instruction.
Write the MIPS assembly code to implement a block copy with this instruction. Estimate the total
cycles necessary for each realization to copy 100-words on the multicycle machine.
Ex. 21. This problem covers 4-bit binary multiplication. Fill in the table for the Product, Multplier
and Multiplicand for each step. You need to provide the DESCRIPTION of the step being
performed (shift left, shift right, add, no add). The value of M (Multiplicand) is 1011, Q
(Multiplier) is isnitially 1010.

Ex. 22. This problem covers floating-point IEEE format.
a) List four floating-point operations that cause NaN to be created?
b) Assuming single precision IEEE 754 format, what decimal number is represent by this word:
1 01111101 00100000000000000000000
(Hint: remember to use the biased form of the exponent.)
Ex. 23. The floating-point format to be used in this problem is an 8-bit IEEE 754 normalized format
with 1 sign bit, 4 exponent bits, and 3 mantissa bits. It is identical to the 32-bit and 64-bit
formats in terms of the meaning of fields and special encodings. The exponent field employs
an bias-7 coding. The bit fields in a number are (sign, exponent, mantissa). Assume that we
use unbiased rounding to the nearest even specified in the IEEE floating point standard.
a) Encode the following numbers the 8-bit IEEE format:
i) 0.0011011
binary

ii) 6.0
decimal

b) Perform the computation 1.011
binary
+ 0.0011011

a) 3 + 12
b) 13 – 2
c) 5 – 6
d) -7 – (-7)
Ex. 26. Define the WiMPY precision IEEE 754 floating point format to be:

where each ’X’ represents one bit. Convert each of the following WiMPY floating point numbers to
decimal:
a) 00000000
b) 11011010
c) 01110000
Ex. 27. This problem covers 4-bit binary unsigned division (similar to Fig. 3.11 in the text). Fill in
the table for the Quotient, Divisor and Dividend for each step. You need to provide the
DESCRIPTION of the step being performed (shift left, shift right, sub). The value of Divisor is
4 (0100, with additional 0000 bits shown for right shift), Dividend is 6 (initially loaded into
the Remainder).

Ex. 28. We’re going to look at some ways in which binary arithmetic can be unexpectedly useful.
For this problem, all numbers will be 8-bit, signed, and in 2’s complement.
a) For x = 8, compute x & (−x). (& here refers to bitwise-and, and − refers to arithmetic negation.)
b) For x = 36, compute x & (−x).
c) Explain what the operation x & (−x) does.
Ex. 29. Data representation
a) Tìm biểu diễn thập phân của số không dấu, dấu phẩy cố định 10110,110
2

b) Tìm biểu diễn không dấu, dấu phẩy cố định của số 106,375
10

c) Có thể đổi một số thập phân bất kz sang dạng nhị phân dấu phẩy cố định mà không làm mất

a) Thiết kế một mạch để trừ 2 số không dấu 32 bit. Mạch này có 2 đầu vào 32 bít và 1 đầu ra 32 bit.
Ngoài ra, mạch có một đầu ra n (negative). N=1 báo hiệu hiệu là số âm và không thể biểu diễn
dưới dạng số không dấu.
b) Thiết kế một mạch để so sánh 2 số có dấu 32 bít a và b. Cả 2 số đều được biểu diễn dưới dạng
dấu và trị số tuyệt đối. Mạch này có 1 đầu ra l (less). Khi l = 1, ta có a < b.
c) Thiết kế một mạch để so sánh 2 số dấu phẩy động độ chính xác đơn.
Ex. 36.
Cho một bộ cộng Ripple-Carry gồm 16 bộ cộng đủ 1 bit như hình sau:

Mỗi cổng có độ trễ 1 đơn vị. Tín hiệu được đưa vào ở thời điểm 0. Tính thời điểm t
ar
các tín hiệu tổng và
tín hiệu nhớ đạt trạng thái ổn định.

Chapter 3.
Ex. 37. For the MIPS datapath shown below, several lines are marked with “X”. For each one:
• Describe in words the negative consequence of cutting this line relative to the working,
unmodified processor.
• Provide a snippet of code that will fail
• Provide a snippet of code that will still work

Ex. 38. Consider the following assembly language code:
I0: ADD R4 = R1 + R0;
I1: SUB R9 = R3 - R4;
I2: ADD R4 = R5 + R6;
I3: LDW R2 = MEM[R3 + 100];
I4: LDW R2 = MEM[R2 + 0];
I5: STW MEM[R4 + 100] = R2;
I6: AND R2 = R2 & R1;
I7: BEQ R9 == R1, Target;

I1 I2
I5 I6

Ex. 39. Structural, data and control hazards typically require a processor pipeline to stall. Listed
below are a series of optimization techniques implemented in a compiler or a processor
pipeline designed to reduce or eliminate stalls due to these hazards. For each of the
following optimization techniques, state which pipeline hazards it addresses and how it
addresses it. Some optimization techniques may address more than one hazard, so be sure
to include explanations for all addressed hazards.
a) Branch Prediction
b) Instruction Scheduling
c) delay slots
d) increasing availability of functional units (ALUs, adders etc)
e) caches
Ex. 40. Branch Prediction. Consider the following sequence of actual outcomes for a single static
branch. T means the branch is taken. N means the branch is not taken. For this question,
assume that this is the only branch in the program.
T T T N T N T T T N T N T T T N T N
f) Assume that we try to predict this sequence with a BHT using one-bit counters. The counters in
the BHT are initialized to the N state. Which of the branches in this sequence would be mis-
predicted?

Ex. 41. The classic 5-stage pipeline seen in Section 4.5 is IF, ID, EX, MEM, WB. This pipeline is

iv) store: DMEM[ R[rs] + signext(offset)] <- R[Rt]; PC <- PC +4;

a) In the table below, indicate the components that determine the critical path for the respective
instruction, in the order that the critical path occurs. If a component is used, but not part of the
critical path of the instruction (ie happens in parallel with another component), it should not be
in the table. The register file is used for reading and for writing; it will appear twice for some
instructions. All instruction begin by reading the PC register with a latency of 2ns.

b) Place the latencies of the components that you have decided for the critical path of each
instruction in the table below. Compute the sum of each of the component latencies for each
instruction.

c) Use the total latency column to derive the following critical path information:
i) Given the data path latencies above, which instruction determines the overall machine
critical path (latency)?
ii) What will be the resultant clock cycle time of the machine based on the critical path
instruction?
iii) What frequency will the machine run?
Ex. 43. This problem covers your knowledge of branch prediction.
The figure below illustrates three possible predictors.

i) Last taken predicts taken when 1
ii) Up-Down (saturating counter) predicts taken when 11 and 10
iii) Automata A3 predicts taken when 11 and 10
Fill out the tables below and on the next page for each branch predictor. The execution pattern for
the branch is NTNNTTTN.
Calculate the prediction rates of the three branch predictors:

1 add $t2, $s1, $sp
2 lw $t1, $t1, 0
3 addi $t2, $t1, 7
4 add $t1, $s2, $sp
5 lw $t1, $t1, 0
6 addi $t1, $t1, 9
7 sub $t1, $t1, $t2
a) What is the load-use latency for the standard MIPS 5-stage pipeline?
b) Once again, using the standard MIPS pipeline, identify whether the value for each register
operand is coming from the bypass or from the register file. For clarity, please write REG or
BYPASS in each box.

c) How many cycles will the program take to execute on the standard MIPS pipeline?
d) Assume, due to circuit constraints, that the bypass wire from the memory stage back to the
execute stage is omitted from the pipeline. What is the load-use latency for this modified
pipeline?
e) Identify whether the value for each register operand is coming from the bypass or from the
register file for the modified pipeline. For clarity, please write REG or BYPASS in each box.

f) How long does the program take to execute on the modified pipeline?
Ex. 48.
Tìm tất cả các phụ thuộc dữ liệu và vẽ đồ thị phụ thuộc của đoạn chương trình dưới đây. Phụ thuộc nào
dẫn tới xung đột dữ liệu nếu không có chuyển tiếp (forwarding). Những xung đột nào có thể giải quyết
bằng chuyển tiếp.
add $2, $5, $4
add $4, $2, $5
sw $5, 100($2)
add $3, $2, $4
Ex. 49.
Xét đoạn chương trình sau:

s4=s2;
}
b) Nếu bộ xử lý có thêm 2 lệnh movz (move if zero) và movn (move if not zero). Ví dụ movz $s1,
$s2, $s3 sẽ sao chép $s2 tới $s1 nếu $s3 là 0. Chuyển đoạn mã C nói trên thành mã hợp ngữ
không dùng câu lệnh nhảy có điều kiện.
c) So sánh thời gian thực hiện của 2 đoạn mã hợp ngữ trên. Đoạn mã nào cần ít thời gian hơn. Nêu
lý do.
Ex. 53. Đoạn mã lệnh sau sẽ được thực hiện trên bộ xử lý có rẽ nhánh chậm (delayed branching)

slt $t0,$s1,$s2
beq $t0,$zero,S_2
j End
addi $s3,$s1,0
S_2: addi $s4,$s2,0
End:

Xác định thứ tự thực hiện các lệnh trong 2 trường hợp rẽ nhánh được thực hiện và không được thực
hiện.
Ex. 54. Xét đoạn mã lệnh sau đây:
1. lw $f1,16($s2)
2. add $f7,$f1,$f5
3. sub $f8,$f1,$f6
4. or $f9,$f5,$f1
5. mult $f5,$f8,$f1
6. bnq $f9,$f7,target
7. add $f1,$f10,$f5
8. sub $f10,$f2,$f7
9. sw $f1,24($s1)
10. sub $f5,$f1,$f10
11. target:
Ex. 3.
a) Why is miss rate not a good metric for evaluating cache performance? What is the
appropriate metric? Give its definition. What is the reason for using a combination of first
and second- level caches rather than using the same chip area for a larger first-level cache?
b) The original motivation for using virtual memory was “compatibility”. What does that mean
in this context? What are two other motivations for using virtual memory?
c) What are the two characteristics of program memory accesses that caches exploit?
d) What are three types of cache misses?
Ex. 4. Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block.
Calculate the following:
a) How many bits are used for the byte offset?
b) How many bits are used for the set (index) field?
c) How many bits are used for the tag?
Ex. 5. Design a 8-way set associative cache that has 16 blocks and 32 bytes per block. Assume a
32 bit address. Calculate the following:
a) How many bits are used for the byte offset?
b) How many bits are used for the set (index) field?
c) How many bits are used for the tag?
Ex. 6. This question covers cache and pipeline performance analysis.
a) Write the formula for the average memory access time assuming one level of cache
memory:
b) For a data cache with a 92% hit rate and a 2-cycle hit latency, calculate the average memory
access latency. Assume that latency to memory and the cache miss penalty together is 124
cycles. Note: The cache must be accessed after memory returns the data.
c) Calculate the performance of a processor taking into account stalls due to data cache and
instruction cache misses. The data cache (for loads and stores) is the same as described in
Part B and 30% of instructions are loads and stores. The instruction cache has a hit rate of
90% with a miss penalty of 50 cycles. Assume the base CPI using a perfect memory system

cache. The cache is physically-indexed cache, and has 64-byte blocks. Assume that there
are 4 extra bits per entry: 1 valid bit, 1 dirty bit, and 2 LRU bits for the replacement policy.
Assume that the physical address is 50 bits wide.
Ex. 10. Caches: Misses and Hits
int i;
int a[1024*1024];
int x=0;
for(i=0;i<1024;i++)
{
x+=a[i]+a[1024*i];
}
Consider the code snippet in code above. Suppose that it is executed on a system with a 2-way set
associative 16KB data cache with 32-byte blocks, 32-bit words, and an LRU replacement policy. Assume
that int is word-sized. Also assume that the address of a is 0x0, that i and x are in registers, and that the
cache is initially empty. How many data cache misses are there? How many hits are there?
Ex. 11. Describe the general characteristics of a program that would exhibit very little temporal
and spatial locality with regard to instruction fetches. Provide an example of such a
program (pseudo-code is fine). Also, describe the cache effects of excessive unrolling. Use
the terms static instructions and dynamic instructions in your description.
Ex. 12. You are given an empty 16K 2-way set-associative LRU-replacement cache with 32 byte
blocks on a machine with 4 byte words and 32-bit addresses. Describe in mathematical
terms a memory read address sequence which yields the following Hit/Miss patterns. If
such a sequence is impossible, state why. Some sample sequences are given:
Hit/Miss pattern
Address sequence being accessed
Miss, Hit, Hit, Miss :
0,0,0,32
Miss, (Hit)*
0, 0*
(Hit)*