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© Digital Integrated Circuits
2nd
Wires
Digital Integrated
Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
The Wire
The Wire
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002
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© Digital Integrated Circuits
2nd
Wires
The Wire
The Wire
transmitters
receivers
schematics
physical
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© Digital Integrated Circuits


Resistive

Inductive
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© Digital Integrated Circuits
2nd
Wires
10 100 1,000 10,000 100,000
Length (u)
No of nets
(Log Scale)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of Interconnect
Nature of Interconnect
Local Interconnect
Global Interconnect
S
Local
= S
Technology
S
Global
= S
Die

db1
C
gd12
C
w
C
g4
C
g3
V
out2
Fanout
Interconnect
V
out
V
in
C
L
Simplified
Model
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© Digital Integrated Circuits
2nd
Wires
Capacitance: The Parallel Plate Model
Capacitance: The Parallel Plate Model
Dielectric
Substrate

Permittivity
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© Digital Integrated Circuits
2nd
Wires
Fringing Capacitance
Fringing Capacitance
W - H/2
H
+
(a)
(b)
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© Digital Integrated Circuits
2nd
Wires
Fringing versus Parallel Plate
Fringing versus Parallel Plate
(from [Bakoglu89])
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© Digital Integrated Circuits
2nd
Wires
Interwire Capacitance
Interwire Capacitance
fringing parallel